AD5161 Analog Devices, AD5161 Datasheet - Page 3

• Manufacturer Part Number: AD5161
• Description: 256-Position SPI/I2C Selectable Digital Potentiometer
• Manufacturer: Analog Devices

256 Position Digital Potentiometer
AD5161 ELECTRICAL CHARACTERISTICS 5K, 10K, 50K, 100K
+3V ±  1 0%, V
Parameter
SPI INTERFACE TIMING CHARACTERISTICS applies to all parts (Notes 6,10)
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CS Setup Time
CS High Pulse Width
CLK Fall to CS Fall Hold Time
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
I
SCL Clock Frequency
t
t
t
t
t
t
t
t
t
t
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5161 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV PrB, 13 DEC’ 02
2
BUF
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
F
R
SU;STO
C INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 6,12)
Fall Time of both SDA & SCL signals
Rise Time of both SDA & SCL signals
Bus free time between
Low Period of SCL Clock
Typicals represent average readings at +25°C and V
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the
relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
V
INL and DNL are measured at V
DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions.
Resistor terminals A,B,W have no limitations on polarity with respect to each other.
Guaranteed by design and not subject to production test.
Measured at the A terminal. A terminal is open circuited in shutdown mode.
P DISS is calculated from (I DD x V DD ). CMOS logic level inputs result in minimum power dissipation
All dynamic characteristics use V
See timing diagram for location of measured values. All input control voltages are specified with t R =t F =2ns(10% to 90% of +3V) and timed from a voltage level of 1.5V. Switching characteristics
are measured using V
The AD5161 contains 2532 transistors. Die Size: 30.7mil x 76.8 mil, 2358sq. mil.
See timing diagram for location of measured values.
High Period of SCL Clock
AB
Setup Time For START Condition t5
Hold Time (repeated START)
Data Hold Time
Data Setup Time
Setup time for STOP Condition
= V
DD
, Wiper (V
A
= +V
W
DD
) = No connect
LOGIC
, V
STOP & START
= +5V.
B
= 0V, -40°C < T
W
DD
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = V
= +5V.
Symbol
t
t
t
t
t
t
t
t
CH
DS
DH
CSS
CSW
CSH0
CSH
CS1
f
t1
t2
t3
t4
t6
t7
t8
t9
t10
SCL
A
,t
DD
CL
< +125°C unless otherwise noted.)
= +5V.
Conditions
Clock level high or low
After this period the first clock pulse is generated
- 3 -
Min
Ω
100
1.3
0.6
1.3
0.6
0.6
0.6
20
15
40
10
5
5
0
0
DD
VERSION
and V
B
Typ
= 0V.
1
(V
Max
400
300
300
0.9
50
DD
AD5161
= +5V ±  1 0%, or
Units
KHz
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns