S29CD016G SPANSION, S29CD016G Datasheet
S29CD016G
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S29CD016G Summary of contents
Page 1
... S29CD016G 16 Megabit (512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory Data Sheet Distinctive Characteristics Architecture Advantages Simultaneous Read/Write operations — Two bank architecture: large bank/ small bank — Data can be read from bank while executing erase/ program functions in other bank — ...
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... General Description The S29CD016G Megabit, 2.5 Volt-only single power supply burst mode flash memory device. The device can be configured for 524,288 double words. The device can also be programmed in standard EPROM programmers. To eliminate bus contention, each device includes separate chip enable (CE#), write enable (WE#), and output enable (OE#) controls ...
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... The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunnelling. The data is programmed using hot electron injection. November 5, 2004 S29CD016_00_A4 detector that automat- CC S29CD016G 3 ...
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... Autoselect Functions ......................................................................................................18 Automatic Sleep Mode (ASM) ........................................................... 18 Standby Mode ...................................................................................................................18 RESET#: Hardware Reset Pin ............................................................ 19 Output Disable Mode ........................................................................... 19 Autoselect Mode ................................................................................... 19 Table 5. S29CD016G Autoselect Codes (High Voltage Meth- od Asynchronous Read Operation (Non-Burst) ...............................20 Figure 1. Asynchronous Read Operation . . . . . . . . . . 21 Synchronous (Burst) Read Operation ............................................. 21 Linear Burst Read Operations ........................................................... 21 Table 6 ...
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... Figure 29. Alternate CE# Controlled Write Operation Tim- ings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 29. Erase and Programming Performance . . . . . 86 Table 30. PQFP and Fortified BGA Pin Capacitance . . . . 86 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 87 PRQ080–80-Lead Plastic Quad Flat Package 87 LAA080–80-ball Fortified Ball Grid Array ( mm) 88 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 89 S29CD016G vs. Frequency . . . . . . . . . . . . 69 CC1 Power-up Diagram ...
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... Min Initial Clock Delay (clock cycles) See Figure 3 Max CE# Access Max OE# Access S29CD016G Synchronous/Burst or Asynchronous 0P (66 MHz) (56 MHz FBGA/ 10 FBGA/ 9.5 PQFP 10 PQFP S29CD016G 0M 0J (40 MHz S29CD016_00_A4 November 5, 2004 ...
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... DQ0–DQ15 A0–A18 November 5, 2004 S29CD016_00_A4 Erase Voltage V IO Generator PGM Voltage Generator Chip Enable Output Enable Logic Y-Decoder Timer X-Decoder Burst Address Counter A0–A18 S29CD016G DQ0 – DQ31 A0–A18 Input/Output Buffers Data Latch Y-Gating Cell Matrix 7 ...
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... STATE RESET# CONTROL & WE# COMMAND CE# REGISTER ADV# DQ0–DQ31 A0–A18 Upper Bank Address Upper Bank (Bank 1) X-Decoder RY/BY# Status Control X-Decoder Lower Bank (Bank 0) Lower Bank Address S29CD016G OE# DQ0–DQ31 S29CD016_00_A4 November 5, 2004 ...
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... MCH November 5, 2004 S29CD016_00_A4 80-pin PQFP Top View S29CD016G 64 DQ15 63 DQ14 62 DQ13 61 DQ12 CCQ 58 DQ11 ...
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... DQ1 DQ5 DQ9 DQ2 DQ6 DQ10 DQ0 DQ4 DQ7 DQ8 DQ3 CCQ SS CCQ S29CD016G DQ20 DQ16 MCH DQ18 IND/WAIT DQ19 OE# WE DQ17 CE WP ...
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... Acceleration input. When taken program and erase operations are accelerated. When not used for acceleration, ACC = Output Buffer Power Supply (1. 2.75 V, 3.6 V tolerant) = Chip Power Supply (2 2. Hardware reset input = Must Connect High ( S29CD016G , the device the two ...
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... Logic Symbols x32 Mode A0–A18 DQ0–DQ31 CLK CE# OE# WE# IND/WAIT# RESET# ADV# RY/BY# ACC WP CCQ S29CD016G 32 S29CD016_00_A4 November 5, 2004 ...
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... S29CD016G0M S29CD016G0J Valid Combinations for Fortified BGA Packages Order Number S29CD016G0P S29CD016G0M S29CD016G0J Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. November 5, 2004 S29CD016_00_A4 ...
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... Don’t care control allows the host system to set the voltage levels that IO S29CD016G Data ADV# Addresses (DQ0–DQ31 OUT HIGH Z X HIGH Z HIGH Z ...
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... ACC ) is the delay from stable addresses and CE –t time and CE# is asserted for at ACC OE 42” for more information. in the DC Characteristics table represents CC1 16, Table 18 on page 50, Table 12 on page S29CD016G Table 1 on 34, and Table 13 15 ...
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... Bank 0 0X, 10 Bank contains details on programming data to the de- and Table 13 on page 36 indicate the address space that “Command Definitions” on page 43 S29CD016G Ordering Option 01 Big Bank Small Bank “DC Characteristics” on “Sector Erase and Program contain details S29CD016_00_A4 November 5, 2004 ...
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... ACC pin, the device automatically en ACC=V ss “Autoselect Mode” on page 18 sections for more information ns. The automatic sleep mode is independent of the ACC or the CLK runs slower than 5 MHz. Note that a new burst op- S29CD016G for more section during any operation other . cc and 17 ...
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... for further discussion of the RESET# pin and its for timing specifications. and V power-up is required to guarantee CC IO and V have reached their steady state CC IO for OE# Operation in Output Disable Mode. S29CD016G ) for read CE during CC7 ““RESET#: S29CD016_00_A4 November 5, 2004 ...
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... DQ7–DQ0. To access the autoselect codes in-system, the host system can issue the autose- lect command via the command. This method does not require V “Command Definitions” on page 43 Table 5. S29CD016G Autoselect Codes (High Voltage Method) Description CE# OE# WE# ...
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... Address 2 Address Figure 1. Asynchronous Read Operation , regardless of the number of CLK cycles applied IL for all valid burst output sequences). The IND/ ) during the last transfer of data during a linear IL for a complete 32-bit data bus interface order. S29CD016G D3 D3 Float S29CD016_00_A4 November 5, 2004 ...
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... WORD# pin) Two Linear Data Transfers Four Linear Data Transfers Eight Linear Data Transfers November 5, 2004 S29CD016_00_A4 Output Data Sequence (Initial Access Address) 0-1 ( 1-0 ( 0-1-2-3 (A1-A0 = 00) 1-2-3-0 (A1-A0 = 01) 2-3-0-1 (A1-A0 = 10) 3-0-1-2 (A1-A0 = 11) 0-1-2-3-4-5-6-7 (A2-A0 = 000) 1-2-3-4-5-6-7-0 (A2-A0 = 001) 2-3-4-5-6-7-0-1 (A2-A0 = 010) 3-4-5-6-7-0-1-2 (A2-A0 = 011) 4-5-6-7-0-1-2-3 (A2-A0 = 100) 5-6-7-0-1-2-3-4 (A2-A0 = 101) 6-7-0-1-2-3-4-5 (A2-A0 = 110) 7-0-1-2-3-4-5-6 (A2-A0 = 111) S29CD016G 21 ...
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... IL before a clock edge, which initiates a new IH or re-issuing a new ADV# pulse. The DQ bus IH , the IND/WAIT# signal floats and IH , the IND/WAIT# signal is driven for more information). Definition S29CD016G . IL . The IL during a burst until it tran- IH S29CD016_00_A4 November 5, 2004 ...
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... Table 8. Burst Initial Access Delay (Sheet CR13 CR12 November 5, 2004 S29CD016_00_A4 Clock Delay Invalid Initial Burst Access CR11 CR10 S29CD016G (Table (CLK cycles ...
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... CLK 3rd CLK 4th CLK Three CLK Delay D0 D1 Four CLK Delay D0 Five CLK Delay Figure 3. Burst Access Timing for more information on the RESET# S29CD016G 5th CLK S29CD016_00_A4 November 5, 2004 ...
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... CR14 CR13 RM ASD IAD3 CR7 CR6 CR5 BS CC Reserved November 5, 2004 S29CD016_00_A4 Table 9 CR12 CR11 CR10 IAD2 IAD1 IAD0 CR4 CR3 CR2 Reserved Reserved BL2 S29CD016G shows the Con- CR9 CR8 DOC WC CR1 CR0 BL1 BL0 25 ...
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... Burst Data Transfer - x32 Linear (device default) 100 = Reserved, burst accesses disabled (asynchronous reads only) 101 = Reserved, burst accesses disabled (asynchronous reads only) 110 = Reserved, burst accesses disabled (asynchronous reads only) 111 = Reserved S29CD016G S29CD016_00_A4 November 5, 2004 ...
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... CR12 CR11 IAD2 IAD1 CR4 CR3 Reserve Reserve Table 12 on page 34 and Table 13 on page Table 12 on page 34 and Table 13 on page S29CD016G CR10 CR9 CR8 IAD0 DOC CR2 CR1 CR0 BL2 BL1 BL0 36. 36. ...
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... PPB Lock is defaulted to power up in the cleared state – meaning the PPBs are changeable. When the device is first powered on the DYBs power up cleared (sectors not pro- tected). The Protection State for each sector is determined by the logical S29CD016G S29CD016_00_A4 November 5, 2004 ...
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... Table 11. Sector Protection Schemes (Sheet DYB PPB November 5, 2004 S29CD016_00_A4 PPB Lock 0 Unprotected—PPB and DYB are changeable 1 Unprotected—PPB not changeable, DYB is changeable 0 0 Protected—PPB and DYB are changeable 0 S29CD016G Sector State 29 ...
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... PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 2 µs delay for each “password check.” This delay PPB Lock 1 1 Protected—PPB not changeable, DYB is changeable 1 S29CD016G Sector State S29CD016_00_A4 November 5, 2004 ...
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... Password Mode Locking Bit, which when set, prevents the Password Verify com- mand from reading the contents of the password on the pins of the device. November 5, 2004 S29CD016_00_A4 53). The password function works in conjunction with the S29CD016G “Password Verify 31 ...
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... Executing the Sector Erase command is permitted when the SecSi Sector is enabled, however, there is no provision for erasing the SecSi Sector with the programming and erase operations of the during the entire pro S29CD016G S29CD016_00_A4 November 5, 2004 ...
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... November 5, 2004 S29CD016_00_A4 the device does not accept any write cycles. This pro- LKO power-up and power-down. The command register and all CC is greater than V . The system must provide the CC LKO . S29CD016G ...
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... SG4 02000h–027FFh SG5 02800h–02FFFh SG6 03000h–037FFh SG7 03800h–03FFFh 04000h–07FFFh SG8 08000h–0BFFFh 0C000h–0FFFFh 10000h–13FFFh 14000h–17FFFh SG9 18000h–1BFFFh 1C000h–1FFFFh S29CD016G , CE WE while IL and x32 Sector Size (KDwords ...
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... SG15 74000h–77FFFh 78000h–7BFFFh SG16 7C000h–7C7FFh SG17 7C800h–7CFFFh SG18 7D000h–7D7FFh SG19 7D800h–7DFFFh SG20 7E000h–7E7FFh SG21 7E800h–7EFFFh SG22 7F000h–7F7FFh SG23 7F800h–7FFFFh S29CD016G Sector Size (KDwords ...
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... SG11 38000h–3BFFFh 3C000h–3FFFFh 40000h–43FFFh 44000h–47FFFh SG12 48000h–4BFFFh 4C000h–4FFFFh 50000h–53FFFh 54000h–57FFFh SG13 58000h–5BFFFh 5C000h–5FFFFh S29CD016G Sector Size (KDwords ...
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... SG15 74000h–77FFFh 78000h–7BFFFh SG16 7C000h–7C7FFh SG17 7C800h–7CFFFh SG18 7D000h–7D7FFh SG19 7D800h–7DFFFh SG20 7E000h–7E7FFh SG21 7E800h–7EFFFh SG22 7F000h–7F7FFh SG23 7F800h–7FFFFh S29CD016G Sector Size (KDwords ...
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... Description Query Unique ASCII string “QRY” Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) S29CD016G 41. To ter- to TTable 17 on page 41. S29CD016_00_A4 November 5, 2004 ...
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... Typical timeout per individual block erase 2 Typical timeout for full chip erase 2 Max. timeout for word/doubleword program 2 Max. timeout for buffer write 2 N Max. timeout per individual block erase 2 Max. timeout for full chip erase 2 S29CD016G pin present) µs N µs (00h = not N ms ...
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... CFI specification or CFI publication 100) Erase Block Region 2 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 3 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 4 Information (refer to the CFI specification or CFI publication 100) S29CD016G N S29CD016_00_A4 November 5, 2004 ...
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... Page Mode Type 00h = Not Supported, 01h = 4 Word Page, 02h = 8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported (DQ7-DQ4: volt in hex, DQ3-DQ0: 100 mV in BCD) ACC (Acceleration) Supply Maximum 00h = Not Supported, (DQ7-DQ4: volt in hex, DQ3-DQ0: 100 mV in BCD) S29CD016G 41 ...
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... Bank Organization (1 byte data at 4Ah is zero XX = Number of banks Bank 1 Region Information (1 byte Number of Sectors in Bank 1 Bank 2 Region Information (1 byte Number of Sectors in Bank 2 Bank 3 Region Information (1 byte Number of Sectors in Bank 3 Bank 4 Region Information (1 byte Number of Sectors in Bank 4 S29CD016G S29CD016_00_A4 November 5, 2004 ...
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... Configuration Register definition. The Burst read cycle consists of an address phase and a corresponding data phase. November 5, 2004 S29CD016_00_A4 for timing diagrams. /t nanoseconds after address becomes stable, CE# be- ACC CE S29CD016G for more infor- for more for “Command Definitions” 43 ...
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... The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further con 27). . However, multiplexing high voltage ID S29CD016G “Initial Access Delay S29CD016_00_A4 November 5, 2004 ...
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... Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required November 5, 2004 S29CD016_00_A4 for information on these status bits.) When the Embedded pump and drain pump, which is limited to 2.5 mA. Because PP S29CD016G “Write Operation 45 ...
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... Figure 21, on page 78 START Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Increment Address Last Address? Programming Completed Figure 4. Program Operation S29CD016G show the Table 29 on and Figure 22, on page 79 No Yes Yes S29CD016_00_A4 November 5, 2004 ...
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... The system is not required to provide any controls or timings during these operations. Note that a hardware reset immediately terminates November 5, 2004 S29CD016_00_A4 for specific CFI codes. S29CD016G “Common Flash 47 ...
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... “DQ7: Data# Polling” on page “DQ6: Toggle Bit I” on “RY/BY#: Ready/Busy#” on illustrates the Embedded Erase Algorithm. See Figure 21, on page 78 and 51). If that occurs, the sector S29CD016G 60) Table 27 on Figure 22, on page 79 and “Sector S29CD016_00_A4 November 5, 2004 ...
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... Table 29 on page 85 and Figure 22, on page 79 for timing diagrams. START Write Erase Command Sequence Data Poll from System Embedded Erase algorithm in progress No Data = FFh? Yes Erasure Completed for erase command sequence. for more information. Figure 5. Erase Operation S29CD016G 63). for parameters, and 49 ...
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... Read operations from the other bank return array data with no latency Table 18 summarizes permis- Program Suspend Erase Suspend Program Resume Erase Resume Read Only Read or Program S29CD016G S29CD016_00_A4 November 5, 2004 ...
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... Flash devices that support CFI, have a “Query Command” that returns information about the device to the system. The Query structure contents are read at the specific address locations following a single system write cycle where: November 5, 2004 S29CD016_00_A4 S29CD016G 51 ...
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... The following commands are unavailable when the SecSi sector is enabled. Issu- ing the following commands while the SecSi sector is enabled results in the command being ignored. 1. Unlock Bypass 2. CFI 3. Accelerated Program for the specific CFI S29CD016G S29CD016_00_A4 November 5, 2004 ...
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... Simultaneous Read/Write operation is disabled when the Password Verify com- mand is executed. Only the password is returned regardless of the bank address. The lower two address bits (A0:A-1) are valid during the Password Verify. Writing the Read/Reset command returns the device back to normal operation. November 5, 2004 S29CD016_00_A4 S29CD016G 53 ...
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... Exiting the PPB Lock Bit Set command is accomplished by writing the Read/Reset command. The PPB Lock Bit Set command is permitted if the SecSi sector is enabled -level SecSi Sector Protection Bit Program Command is CC S29CD016G S29CD016_00_A4 November 5, 2004 ...
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... the PPB Lock Bit is set and the corresponding PPB is set for the sector, the PPB Program command does not execute and the command times out without programming the PPB. November 5, 2004 S29CD016_00_A4 S29CD016G 55 ...
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... PPB Lock Bit Status The programming of the PPB Lock Bit for a given sector can be verified by writing a PPB Lock Bit status verify command to the device S29CD016G S29CD016_00_A4 November 5, 2004 ...
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... ADV# indicates the status.) If the DQ6 toggle bit toggles with either OE# or CE#, the non-volatile bit program or erase operation is in progress. When DQ6 stops toggling, the value of the non- volatile bit is available on DQ0. November 5, 2004 S29CD016_00_A4 S29CD016G 57 ...
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... ACC must 17. Command is ignored during any Embedded Program, Embedded Erase, or Suspend operation. 18. The Unlock Bypass Entry command is required prior to any Unlock Bypass operation. The Unlock Bypass Reset command is required to return to the read mode. S29CD016G Fourth Fifth Sixth Addr Data ...
Page 59
... PPBs. 11. In the fourth cycle, 00h indicates PPB set; 01h indicates PPB not set. 12. The status of additional PPBs and DYBs may be read (following the fourth cycle) without reissuing the entire command sequence. S29CD016G Fourth Fifth Sixth Data Addr ...
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... DQ7 data polling Table 21 on page 65 shows the outputs for Data# Polling on DQ7. Figure 24, on page 80 S29CD016G and the following Figure 6, on shows the S29CD016_00_A4 November 5, 2004 ...
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... DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. November 5, 2004 S29CD016_00_A4 START Read DQ7–DQ0 Addr = VA Yes DQ7 = Data? No DQ5 = 1? Yes Read DQ7–DQ0 Addr = VA Yes DQ7 = Data? No PASS FAIL Figure 6. Data# Polling Algorithm S29CD016G 61 ...
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... RESET# pin returns external pull-up resistor is CC level since the output is an open drain. IH shows the outputs for RY/BY#. 75, Figure 21, on page 78 and Figure 23, on page 79 S29CD016G . IH Figure 16, on page 73, shows “DQ7: Data# Polling” S29CD016_00_A4 November 5, 2004 ...
Page 63
... See subsection. Figure 25, on page 80 Figure 26, on page 81 shows the differences be- Figure 27, on page 81 for the following discussion. Whenever the sys- S29CD016G Figure 7, on “Read- Figure 25, on shows the shows shows the timing 63 ...
Page 64
... START Read Byte (DQ0-DQ7) Address = VA Read Byte (Note 1) (DQ0-DQ7) Address = VA No DQ6 = Toggle? Yes No DQ5 = 1? Yes Read Byte Twice (Notes (DQ 0-DQ7 Adrdess = VA No DQ6 = Toggle? Yes FAIL Figure 7. Toggle Bit Algorithm S29CD016G Figure 7). PASS S29CD016_00_A4 November 5, 2004 ...
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... Table 21 on page 65 Table 21. Write Operation Status DQ7 DQ5 (Note 2) DQ6 (Note 1) DQ7# Toggle 0 0 Toggle toggle 0 Data Data Data DQ7# Toggle 0 for more information. S29CD016G “Sector shows the DQ2 DQ3 (Note 2) RY/BY# N/A No toggle 0 1 Toggle 0 N/A Toggle 1 Data Data 1 N/A N ...
Page 66
... 2.0 V for periods ns. See Figure +2 +0.5 V 2.0 V Figure 9. Maximum Positive Overshoot Waveform ) . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85° –40°C to +125°C A S29CD016G S29CD016_00_A4 November 5, 2004 ...
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... IL SS ACC = 2 4.0 mA min min I = –100 µ min = CCmax S29CD016G Min Typ Max Unit ±1.0 µA –25 µA 35 µA µA ±1 µ µ ...
Page 68
... Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 Note -40 ° 1500 2000 2500 Time Frequency in MHz Figure 11. Typical I vs. Frequency CC1 S29CD016G 3000 3500 4000 2 S29CD016_00_A4 November 5, 2004 ...
Page 69
... Test C L Figure 12. Test Setup Table 23. Test Specifications 40 Mhz (OJ), 56 Mhz (OM) Inputs Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Z) Measurement Level S29CD016G 66 Mhz (OP) Unit 1 TTL gate 30 100 5 0.0 V – ...
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... IO t RESET# Low Hold Time RSTH IOP RESET# Figure 14 Test Setup Min Min Min t VCS t VIOS t RSTH and V Power-up Diagram CC IO S29CD016G Speed Unit 50 µs 50 µs 50 µs S29CD016_00_A4 November 5, 2004 ...
Page 71
... Table 24. Asynchronous Read Operations Test Setup Read Toggle and Data# Polling Table 23 on page 69 for test specifications t RC Addresses Stable t ACC OEH t CE HIGH Z S29CD016G Speed Options 66 Mhz 55 Mhz 40 Mhz (OP) (OM) (OJ) Max Max Max ...
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... Min Min Max 9.5 PQFP Min Max Min Max Max Max Min Min Min Min Min Min Min Min Min Min Max Min Max Max Min S29CD016G Speed Options 56 Mhz 40 Mhz (0M) (0J) Unit 9 FBGA 10 FBGA PQFP 6 ns 1.5 1.5 1 ...
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... Characteristics CE# CLK t ADVCS ADV# t ACS Addresses Aa Data OE#* IND# November 5, 2004 S29CD016_00_A4 CES t ADVCH t BDH t t BACC ACH IACC t OE Figure 16. Burst Mode Read (x32 Mode) S29CD016G t CEZ OEZ 73 ...
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... Stable Address t WC Valid Data OEH t WPH t ADVCS ACS ACH Valid Address ADVCH t WCKS WADVH WADVH2 S29CD016G EHQZ Data Out S29CD016_00_A4 November 5, 2004 ...
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... November 5, 2004 S29CD016_00_A4 Table 26. Hardware Reset (RESET#) Test Setup Ready Reset Timing to Bank Executing Embedded Algorithm t Ready t RP Figure 19. RESET# Timings S29CD016G All Speed Options Max 11 Max 500 Min 500 Min 50 Min Unit µs ...
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... AC Characteristics Data WE# WP# RY/BY Program/Erase Command WPWS Valid WP Figure 20. WP# Timing S29CD016G t WPRH S29CD016_00_A4 November 5, 2004 ...
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... Table 27. Erase/Program Operations Min Min Min Min Min Min Min Min Min Min Min Min Min Double-Word Typ Typ Min Min Max Min Max S29CD016G All Speed Options Unit ...
Page 78
... WPH A0h t BUSY is the true data at the program address. OUT Figure 21. Program Operation Timings S29CD016G Read Status Data (last two cycles WHWH1 D Statu OUT t RB S29CD016_00_A4 November 5, 2004 ...
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... Valid RA t ACC OEH GHWL t WPH Valid Out t SR/W Read Cycle Figure 23. Back-to-back Cycle Timings S29CD016G Read Status Data WHWH2 In Complete Progress t RB Table 21 on page Valid PA Valid PA t CPH t CP Valid Valid In ...
Page 80
... Status Data Figure 24. Data# Polling Timings (During Embedded Algorithms Valid Status Valid Status (first read) (second read) Figure 25. Toggle Bit Timings (During Embedded Algorithms) S29CD016G High Z Valid Data True High Z True Valid Data VA VA Valid Status Valid Data ...
Page 81
... Data polling requires burst access time delay. Figure 27. Synchronous Data Polling Timing/Toggle Bit Timings November 5, 2004 S29CD016_00_A4 Enter Erase Suspend Program Erase Erase Suspend Suspend Read Program Status Data S29CD016G Erase Resume Erase Erase Complete Read t OE Status Data 81 ...
Page 82
... Command for sector protect verify is 48h. Command for sector unprotect verify is 40h. Figure 28. Sector Protect/Unprotect Timing Diagram Valid* 60h/68h** 40h/48h*** Sector Protect: 150 µs Sector Unprotect S29CD016G Valid* Valid* Verify Status S29CD016_00_A4 November 5, 2004 ...
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... See the section for more information. November 5, 2004 S29CD016_00_A4 Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Double-Word Typ Typ S29CD016G All Speed Options Unit ...
Page 84
... SA for sector erase 555 for chip erase Data# Polling WPH GHEL t t WHWH1 CPH t BUSY for program PD for program 55 for erase 30 for sector erase 10 for chip erase S29CD016G PA DQ7# D OUT = data OUT S29CD016_00_A4 November 5, 2004 ...
Page 85
... C, 2 2.5 V, 1,000,000 cycles. CC and Table 20 on page 59 for further information on command definitions. Test Setup OUT V IN S29CD016G Unit Comments s Excludes 00h programming prior to erasure (Note 4) s µs µs Excludes system level s overhead (Note 100,000 cycles. Additionally, CC ...
Page 86
... LEAD COPLANARITY SHALL BE WITHIN: (REFER TO 06-500 0.10 mm FOR DEVICES WITH LEAD PITCH OF 0. 0.076 mm FOR DEVICES WITH LEAD PITCH OF 0.50 mm. COPLANARITY IS MEASURED PER SPECIFICATION 06-500. 9. HALF SPAN (CENTER OF PACKAGE TO LEAD TIP) SHALL BE WITHIN ±0.0085". S29CD016G 0.20 MIN. FLAT SHOULDER 7˚ TYP. A 7˚ ccc TYP ...
Page 87
... OR E DIMENSION, RESPECTIVELY 0.000. BALL COUNT WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW , e/2 BALL DIAMETER 8. N/A BALL PITCH - D DIRECTION 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALL PITCH - E DIRECTION BALLS. SOLDER BALL PLACEMENT S29CD016G ...
Page 88
... Table 6: “(x16)” removed from header row. IND/Wait# Operation in Linear Mode Figure 2 - “Address 2” removed. Initial Burst Access Delay Control Figure 3 - Valid Address line changed. Notes - Clock cycles updated S29CD016G S29CD016_00_A4 November 5, 2004 ...
Page 89
... TWPH row added, TWADVH row added, TWCKS row added. Physical Dimensions Latchup characteristics deleted. Pin Description “WAIT# Provides data valid feedback only when the burst length is set to continuous.” Removed from document. November 5, 2004 S29CD016_00_A4 S29CD016G 89 ...
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... Change Address text column. SecSI Sector Entry Command Changed address text in this paragraph Figure 18 Changed time spec call out from Table 27 Added new row for WADVH2 t WADVH2 S29CD016G S29CD016_00_A4 November 5, 2004 ...
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... Copyright ©2004 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies. November 5, 2004 S29CD016_00_A4 any S29CD016G use that includes fatal risks or dangers that, unless for any use ...