74HC75 Philips, 74HC75 Datasheet - Page 2

• Manufacturer Part Number: 74HC75
• Description: Quad bistable transparent latch
• Manufacturer: Philips

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT75 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
ORDERING INFORMATION
See
December 1990
t
C
C
PHL
SYMBOL
Complementary Q and Q outputs
V
Output capability: standard
I
Quad bistable transparent latch
I
PD
CC
CC
f
f
C
V
For HCT the condition is V
i
o
“74HC/HCT/HCU/HCMOS Logic Package Information”
/ t
CC
PD
L
category: MSI
= output frequency in MHz
= input frequency in MHz
(C
PLH
and GND on the centre pins
= output load capacitance in pF
P
= supply voltage in V
L
is used to determine the dynamic power dissipation (P
D
= C
V
amb
CC
propagation delay
input capacitance
power dissipation capacitance per latch
PD
2
nD to nQ, nQ
LE
= 25 C; t
n-n
V
f
o
CC
) = sum of outputs
to nQ, nQ
2
f
r
i
= t
PARAMETER
I
I
f
= GND to V
= GND to V
= 6 ns
(C
L
V
CC
2
CC
CC
f
o
1.5 V
) where:
C
notes 1 and 2
2
.
L
The 74HC/HCT75 have four bistable latches. The two
latches are simultaneously controlled by one of two active
HIGH enable inputs (LE
HIGH, the data enters the latches and appears at the nQ
outputs. The nQ outputs follow the data inputs (nD) as long
as LE
one set-up time prior to the HIGH-to-LOW transition of the
LE
remain stable as long as the LE
= 15 pF; V
D
n-n
CONDITIONS
in W):
n-n
will be stored in the latches. The latched outputs
is HIGH (transparent). The data on the nD inputs
CC
= 5 V
1-2
11
11
3.5
42
and LE
HC
TYPICAL
n-n
3-4
Product specification
74HC/HCT75
is LOW.
). When LE
12
11
3.5
42
HCT
ns
ns
pF
pF
n-n
UNIT
is