74LV4053 Philips, 74LV4053 Datasheet - Page 2

• Manufacturer Part Number: 74LV4053
• Description: Triple 2-channel analog multiplexer/demultiplexer
• Manufacturer: Philips

1.
2.
Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
NOTES:
ORDERING INFORMATION
PIN CONFIGURATION
1998 Jun 23
t
t
C
C
C
16-Pin Plastic DIL
16-Pin Plastic SO
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
PZH
PHZ
SYMBOL
Optimized for low voltage applications: 1.0 to 6.0 V
Accepts TTL input levels between V
Low typ “ON” resistance:
100 W at V
150 W at V
240 W at V
Logic level translation: to enable 3 V logic to communicate with
V analog signals
Typical “break before make” built in
Output capability: non-standard
I
Triple 2-channel analog multiplexer/demultiplexer
I
PD
S
CC
C
P
f
f
V
The condition is V
/t
/t
i
o
category: MSI
D
CC
PD
= input frequency in MHz; C
PZL
PLZ
= output frequency in MHz; C
((C
= C
is used to determine the dynamic power dissipation (P
= supply voltage in V;
L
PD
+C
PACKAGES
cc
cc
cc
amb
Turn “ON” time
E to V
S
Turn “OFF” time
E to V
S
Input capacitance
Power dissipation capacitance per switch
Maximum switch capacitance
independent (Y) common (Z)
S
– V
– V
– V
)
n
n
V
= 25 C; t
to V
to V
CC
EE
EE
EE
V
GND
CC
OS
OS
2
2Y
2Y
3Y
3Y
V
OS
OS
= 2.0 V
= 4.5 V
= 3.0 V
3Z
EE
I
E
2
1
0
1
0
= GND to V
f
i
1
2
3
4
8
5
6
7
) ((C
r
f
=t
o
PARAMETER
) = sum of the outputs.
f
2.5 ns
L +
L
CC
= output load capacity in pF;
S
C
CC
= maximum switch capacitance in pF;
.
S
TEMPERATURE RANGE
)
SV01687
= 2.7 V and V
16
15
14
13
12
10
11
9
V
–40 C to +125 C
–40 C to +125 C
–40 C to +125 C
–40 C to +125 C
CC
V
2Z
1Z
1Y
1Y
S
S
S
CC
1
2
3
2
1
0
f
o
) where:
CC
= 3.6 V
C
R
V
See Notes 1 and 2
L
L
CC
= 15 pF
= 1KW
= 3.3 V
D
3
in W)
OUTSIDE NORTH AMERICA
2
DESCRIPTION
The 74LV4053 is a low-voltage CMOS device and is pin and
function compatible with the 74HC/HCT4053.
The 74LV4053 is a triple 2-channel analog multiplexer/demultiplexer with
a common enable input (E). Each multiplexer/demultiplexer has two
independent inputs/outputs (nY
and three digital select inputs (S
With E LOW, one of the two switches is selected (low impedance
ON-state) by S
impedance OFF-states, independent of S
V
(S
analog inputs/outputs (nY
as a positive limit and V
exceed 6.0 V. For operation as a digital multiplexer/demultiplexer, V
is connected to GND (typically ground).
PIN DESCRIPTION
74LV4053 PW
74LV4053 DB
PIN NUMBER
2, 1
5, 3
6
7
8
11, 10, 9
12, 13
14, 15, 4
16
CC
CONDITIONS
1
74LV4053 N
74LV4053 D
, to S
and GND are the supply voltage pins for the digital control inputs
3
, and E). The V
1
to S
2Y
3Y
E
V
GND
S
1Y
1Z to 3Z
V
EE
1
CC
SYMBOL
3
0
0
0
to S
, 2Y
, 3Y
, 1Y
With E HIGH, all switches are in the high
EE
CC
0
3
, to nY
as a negative limit. V
1
1
1
NORTH AMERICA
to GND ranges are 1.0 to 6.0 V. The
74LV4053PW DH
0
74LV4053 DB
74LV4053 N
74LV4053 D
1
to nY
to S
1
, and nZ) can swing between V
Independent inputs/outputs
Independent inputs/outputs
Enable input (active LOW)
Negative supply voltage
Ground (0 V)
Select inputs
Independent inputs/outputs
Common inputs/outputs
Positive supply voltage
3
1
).
), a common input/output (nZ)
TYPICAL
1
and S
16
20
17
16
36
5
8
FUNCTION
3.5
Product specification
CC
74LV4053
3
- V
.
PKG. DWG. #
853-2000 19618
EE
SOT109-1
SOT338-1
SOT403-1
SOT38-1
may not
UNIT
ns
ns
pF
F
CC
EE