MAX1168 Maxim, MAX1168 Datasheet
MAX1168
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MAX1168 Summary of contents
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... MAX1167 is available in a 16-pin QSOP package and the MAX1168 is available in a 24-pin QSOP package. Both devices are guaranteed over the commercial (0°C to +70°C) and extended (-40°C to +85°C) temperature ranges. Use the MAX1168 evaluation kit to evaluate the MAX1168. Motor Control Industrial Process Control ...
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... Maximum Current into Any Pin............................................50mA Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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Multichannel, 16-Bit, 200ksps Analog-to-Digital ELECTRICAL CHARACTERISTICS (continued) ( +4.75V to +5.25V SCLK = +4.096V unless otherwise noted. Typical values are MIN MAX PARAMETER SYMBOL CONVERSION ...
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters ELECTRICAL CHARACTERISTICS (continued) ( +4.75V to +5.25V SCLK = +4.096V unless otherwise noted. Typical values are MIN MAX PARAMETER SYMBOL ...
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Multichannel, 16-Bit, 200ksps Analog-to-Digital ELECTRICAL CHARACTERISTICS (continued) ( +4.75V to +5.25V SCLK = +4.096V unless otherwise noted. Typical values are MIN MAX PARAMETER SYMBOL I ...
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters TIMING CHARACTERISTICS (Figures and 16) (AV = +4.75V to +5.25V +2.7V to +5.25V (200ksps), external V = +4.096V REF A PARAMETER SYMBOL Acquisition Time ...
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Multichannel, 16-Bit, 200ksps Analog-to-Digital ( +5V 4.8MHz SCLK INL vs. CODE 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 0 16384 32768 49152 65536 CODE SINAD vs. FREQUENCY 100 ...
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters ( +5V 4.8MHz SCLK DIGITAL SUPPLY CURRENT vs. DIGITAL SUPPLY VOLTAGE ...
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Multichannel, 16-Bit, 200ksps Analog-to-Digital ( +5V 4.8MHz SCLK OFFSET ERROR vs. SUPPLY VOLTAGE 200 V = +4.096V REF 100 0 -100 -200 -300 -400 4.75 4.85 4.95 5.05 5.15 AV (V) DD ...
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... FUNCTION Serial Data Output. Data changes state on SCLK’s falling edge in SPI/QSPI/MICROWIRE mode and on SCLK’s rising edge in DSP mode (MAX1168 only). DOUT is high impedance when CS is high. Serial Clock Input. SCLK drives the conversion process in external clock mode and clocks data out ...
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... ADCs feature a successive-approximation ADC, auto- matic power-down, integrated +4.096V reference, and a high-speed SPI/QSPI/MICROWIRE-compatible interface. A DSPR input and DSPX output allow the MAX1168 to communicate with digital signal processors (DSPs) with no external glue logic. The MAX1167/MAX1168 operate with a single +5V analog supply and feature a separate digital supply, allowing direct interfacing with +2 ...
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... If the input signal’s source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. The acquisition time ( the maximum time the device takes to acquire ACQ the signal. Use the following formula to calculate acqui- sition time: ...
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... CS DSEL DSPR DIN Figure 4. MAX1168 Functional Diagram The MAX1168 features a 16-bit-wide data-transfer mode that includes a longer acquisition time (11.5 clock cycles). Longer acquisition times are useful in applications with input source resistances greater than 1kΩ. Noise increases when using large source resis- tances. To improve the input signal bandwidth under AC conditions, drive AIN_ with a wideband buffer (> ...
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... GND Figure 6. MAX1168 T ypical Operating Circuit In addition to the standard 3-wire serial interface modes, the MAX1168 includes a DSPR input and a DSPX output for communicating with DSPs in external clock mode and a DSEL input to determine 8-bit-wide or 16-bit-wide data- ZERO transfer mode. When not using the MAX1168 in the DSP ...
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... Table 4. MAX1168 Scan Mode, Internal Clock Only (Not for DSP Mode) ACTION Single channel, no scan Sequentially scan channels 0 through N (N ≤ 7) Sequentially scan channels 4 through N (4 ≤ N ≤ 7) Scan channel N eight times Table 5. Power-Down Modes BIT2 ...
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... Using an external reference requires no extra wake-up time. External Clock 8-Bit-Wide Data-Transfer Mode Force DSPR high and DSEL low (MAX1168) for SPI/ QSPI/MICROWIRE interface mode. The falling edge of CS wakes the analog circuitry and allows SCLK to clock in data. Ensure the duty cycle on SCLK is between 45% and 55% when operating at 4 ...
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... External Clock 16-Bit-Wide Data-Transfer Mode Force DSPR high and DSEL high for SPI/QSPI/ MICROWIRE interface mode. Logic high at DSEL allows the MAX1168 to transfer data in 16-bit-wide words. The acquisition time is extended an extra eight SCLK cycles in the 16-bit-wide data-transfer mode. The falling edge of CS wakes the analog circuitry and allows SCLK to clock in data ...
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... Converters SCLK MSB LSB DIN 0 DOUT DSPR DSEL ADC STATE t ACQ , X = DON T CARE Figure 11. SPI External Clock Mode, 16-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only SCLK INTERNAL CLK MSB LSB DIN 1 DOUT EOC ADC STATE , X = DON T CARE DSPR = DV , DSEL = GND (MAX1168 ONLY) DD Figure 12 ...
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... INTERNAL CLK DIN DATA DOUT EOC ADC STATE CONFIGURATION , X = DON T CARE DSPR = DSEL = DV DD Figure 13. SPI Internal Clock Mode,16-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only SCLK INTERNAL CLK MSB LSB DIN 1 DOUT EOC ADC STATE ...
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... INTERNAL CLK DATA DIN DOUT EOC ADC STATE , X = DON T CARE Figure 15. SPI Internal Clock Mode, 16-Bit Data-Transfer Mode, Scan Mode for Two Conversions, Conversion Timing (MAX1168 Only) t CSW DSPR t CSS SCLK DIN DOUT Figure 16. Detailed DSP-Interface Timing (MAX1168 Only) ...
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... Multichannel, 16-Bit, 200ksps Analog-to-Digital CS DSPR 1 SCLK MSB DIN DOUT DSPX ADC STATE t ACQ Figure 17. DSP External Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only) CS DSPR 1 SCLK MSB DIN DOUT DSPX ADC STATE , X = DON T CARE Figure 18. DSP External Clock Mode, 16-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only) are shut down on the EOC high-to-low transition ...
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... SCLK cycles are needed. Extra clock pulses 3/2 LSB occurring after the conversion result has been clocked out and prior to the next rising edge of DSPR, cause zeros to be clocked out of DOUT. The MAX1168 exter- , REF nal clock, DSP 8-bit-wide data-transfer mode requires 24 clock cycles to complete ...
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... The MAX1168 samples the input on the rising edge of the 15th clock cycle. On the rising edge of the 16th clock cycle, the MAX1168 outputs a frame sync pulse at DSPX. The frame sync pulse alerts the DSP that the conversion results are about to be output at DOUT (MSB first) starting on the rising edge of the 17th clock pulse ...
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... When using the internal clock mode, the internal oscilla- tor controls the acquisition and conversion processes, while the external oscillator shifts data in and out of the MAX1167/MAX1168. Turn off the external clock (SCLK) when the internal clock realize lowest noise per- formance. The internal clock remains off in external clock mode ...
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... AIN has a typical bandwidth of 4MHz. Avoid degrading dynamic performance by choosing an amplifier with distortion much less than the total har- monic distortion of the MAX1167/MAX1168 at the fre- quencies of interest (THD = -100dB at 1kHz). If the chosen amplifier has insufficient common-mode rejec- tion, which results in degraded THD performance, use the inverting configuration (positive input grounded) to eliminate errors from this source ...
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... SPI and MICROWIRE Interfaces When using the SPI (Figure 20a) or MICROWIRE (Figure 20b) interfaces, set CPOL = 0 and CPHA = 0. Drive CS low to power on the MAX1167/MAX1168 before starting a conversion (Figure 20c). Three consecutive 8-bit-wide readings are necessary to obtain the entire 16-bit result from the ADC. DOUT data transitions on the serial clock’s falling edge ...
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... The DSP mode of the MAX1168 only operates in exter- nal clock mode. Figure 23 shows a typical DSP interface connection to the MAX1168. Use the same oscillator as the DSP to provide the clock signal for the MAX1168. The DSP provides the falling edge wake the MAX1168. The MAX1168 detects the state of DSPR on the falling edge of CS (Figure 17) ...
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... Use printed circuit (PC) boards with separate analog and digital ground planes. Do not use wire-wrap boards. Connect the two ground planes together at the MAX1167/MAX1168 AGND terminal. Isolate the digital supply from the analog with a low-value resistor (10Ω) or ferrite bead when the analog and digital supplies come from the same source (Figure 25) ...
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... Ordering Information (continued) PART TEMP RANGE MAX1168ACEG 0°C to +70°C MAX1168BCEG 0°C to +70°C MAX1168CCEG 0°C to +70°C MAX1168AEEG* -40°C to +85°C MAX1168BEEG* -40°C to +85°C MAX1168CEEG* -40°C to +85°C *Future product—contact factory for availability. TOP VIEW DOUT 1 SCLK 2 DIN 3 EOC 4 AIN0 ...
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... For the latest package outline information www.maxim-ic.com/packages.) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...