MAX1358B Maxim Integrated Products, MAX1358B Datasheet - Page 53

• Manufacturer Part Number: MAX1358B
• Description: Data-Acquisition System
• Manufacturer: Maxim Integrated Products

DataSheet.in
Table 16. UPIO Mode Configuration
Note: When multiple UPIO inputs are configured for the same input function, the inputs are ORed together.
16-Bit, Data-Acquisition System with ADC, DACs,
UP2MD<3:0>, UP1MD<3:0>
UPIOs, RTC, Voltage Monitors, and Temp Sensor
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
UP4MD<3:0>,
UP3MD<3:0>,
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
______________________________________________________________________________________
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AL_DAY or AL_DAY
SPDT1 or SPDT1
SPDT2 or SPDT2
SLEEP or SLEEP
SHDN or SHDN
DRDY or DRDY
PWM or PWM
SWA or SWA
SWB or SWB
WU or WU
Reserved
Reserved
MODE
GPO
GPI
General-purpose digital input. Active edges detected by UPR_ or UPF_
status register bits. ALH_ has no effect with this setting.
General-purpose digital output. Logic level set by LL_ bit. ALH_ has no
effect with this setting.
Digital input. DAC A buffer switch control. See the SWA bit description in
the SW_CTRL Register section.
Digital input. DAC B buffer switch control. See the SWB bit description in
the SW_CTRL Register section.
Digital input. SPDT1 switch control. See the SPDT1<1:0> bit description in the
SW_CTRL Register section.
Digital input. SPDT2 switch control. See the SPDT2<1:0> bit description in the
SW_CTRL Register section.
Sleep-mode digital input. Overrides power-control register and puts the
part into sleep mode when asserted. The clock buffers must be powered
down separately. When deasserted, power mode is determined by the
SHDN bit.
Wake-up digital input. Asserted edge clears SHDN bit.
Reserved. Do not use these settings.
PWM digital output. Signal defined by the PWM_CTRL register. PWM on
(or high or “1”); assertion level defined by the ALH_ bit. When PWM is
disabled (PWME = 0), the UPIO pin idles high (DV
ALH = 1, and low (DGND) if ALH = 0.
Power-supply shutdown digital output. Equivalent to SHDN bit. Power-on
default of GPI with pullup ensures initial power-supply turn-on when UPIO
is connected to a power supply with a SHDN input.
RTC alarm digital output. Asserts for time-of-day alarm events; equivalent
to ALD in STATUS register.
ADC data-ready digital output. Asserts when analog-to-digital conversion
or calibration completes. Not masked by MADD bit.
Reserved. Do not use these settings.
DESCRIPTION
DD
or CPOUT) if
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