X9421 Xicor, X9421 Datasheet - Page 7

• Manufacturer Part Number: X9421
• Description: Single Digitally Controlled (XDCP) Potentiometer
• Manufacturer: Xicor

X9421
The four high order bits of the instruction byte specify
the operation. The next two bits (R
of the four registers that is to be acted upon when a
register oriented instruction is issued. The last two bits
are defined as 0.
Two of the eight instructions are two bytes in length and
end with the transmission of the instruction byte. These
instructions are:
– XFR Data Register to Wiper Counter Register —This
– XFR Wiper Counter Register to Data Register—This
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by t
from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of t
between the potentiometer and one of its associated
registers.
Figure 4. Two-Byte Instruction Sequence
REV 1.1.6 8/1/02
instruction transfers the contents of one specified
Data Register to the Wiper Counter Register.
instruction transfers the contents of the Wiper
Counter Register to the specified associated Data
Register.
WR
SCK
CS
SI
to complete. The transfer can occur
0
1
1
and R
0
WRL
1
0
) select one
. A transfer
1
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1
0
A0
Five instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9421; either between the host and one
of the Data Registers or directly between the host and
the WCR. These instructions are:
– Read Wiper Counter Register—read the current
– Write Wiper Counter Register—change current wiper
– Read Data Register—read the contents of the
– Write Data Register—write a new value to the
– Read Status—This command returns the contents of
The sequence of these operations is shown in Figure 5
and Figure 6.
The final command is Increment/Decrement. It is
different from the other commands, because it’s length
is indeterminate. Once the command is issued, the
master can clock the wiper up and/or down in one
resistor segment steps; thereby, providing a fine tuning
capability to the host. For each SCK clock pulse (t
while SI is HIGH, the selected wiper will move one
resistor segment towards the V
for each SCK clock pulse while SI is LOW, the selected
wiper will move one resistor segment towards the
V
and timing for this operation are shown in Figure 7 and
Figure 8.
L
I3
wiper position of the pot,
position of the pot,
selected data register;
selected data register.
the WIP bit which indicates if the internal write cycle
is in progress.
/R
L
I2
terminal. A detailed illustration of the sequence
I1
I0
Characteristics subject to change without notice.
R1 R0
0
0
H
/R
H
terminal. Similarly,
7 of 21
HIGH
)