SAA7366T Philips Semiconductors, SAA7366T Datasheet - Page 7

• Manufacturer Part Number: SAA7366T
• Description: Bitstream conversion ADC for digital audio systems
• Manufacturer: Philips Semiconductors

Philips Semiconductors
During standby the following occurs:
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Notes
1. V
2. Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor with a rise time of 15 ns.
3. Equivalent to discharging a 200 pF capacitor via a 2.5 H series inductor.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
CHARACTERISTICS
V
May 1994
V
V
I
V
I
I
I
T
T
V
V
Supply
V
I
V
I
P
IK
O
DDtot
SStot
DDA
DDD
DDD
SYMBOL
amb
stg
The internal logic clock is disabled
The serial interface pins are forced to high impedance
The OVLD output is forced LOW
The analog circuitry is disabled
The nominal external analog node voltages are
maintained by a low-power circuit. This feature ensures
a fast recovery from standby mode.
DDA
I
O
es1
es2
DDA
DDD
tot
SYMBOL
Bitstream conversion ADC for
digital audio systems
SSD
= 3.4 to 5.5 V; V
and V
analog supply voltage
DC input voltage
DC input diode current
DC output voltage
DC output source or sink current
total DC supply current
total DC supply current
operating ambient temperature
storage temperature
electrostatic handling
electrostatic handling
SSA
analog supply voltage
analog supply current
digital supply voltage
digital supply current
total power consumption
pins must be externally connected to a common potential.
DDA
PARAMETER
PARAMETER
= 4.5 to 5.5 V; T
amb
= 40 to +85 C; f
f
f
f
s
s
s
CONDITIONS
= 48 kHz
= 48 kHz
= 48 kHz
note 1
note 2
note 3
7
CONDITIONS
On a LOW-to-HIGH transition the device reverts back to its
normal function. This process takes approximately 32
system clock cycles. Before SDO is enabled the output
data is forced LOW. SDO remains LOW until good data is
available from the decimation filter.
The STD pin has a Schmitt-trigger input. A simple
power-on reset function can be effected using an external
capacitor to V
s
= 18 to 53 kHz; unless otherwise specified.
4.5
3.4
MIN.
SSD
and resistor to V
0.5
0.5
0.5
40
65
2000
200
5.0
13
5.0
56
345
MIN.
TYP.
+6.5
+6.5
V
+85
+150
+2000
+200
Preliminary specification
20
20
0.5
0.5
DD
DDD
5.5
5.5
MAX.
+ 0.5
MAX.
.
SAA7366
mA
mA
A
A
V
V
V
V
V
C
C
UNIT
V
mA
V
mA
mW
UNIT