ADMC300-PB Analog Devices, ADMC300-PB Datasheet - Page 15

• Manufacturer Part Number: ADMC300-PB
• Description: High Performance DSP-Based Motor Controller
• Manufacturer: Analog Devices

register is a 7-bit register so that the ADC sample period is
effectively subdivided into 128 equal time slices. The value
written to the ADCSYNC register is the number of such time
slices before the PWMSYNC pulse that the CONVST pulse is
active. In other words, the occurrence of the CONVST pulse
lags the PWMSYNC pulse of Figure 9 (b) by a time, T
that can be expressed as a fraction of the ADC update period:
Therefore, for the case where ADCDIVA is 0x180 and ADCSYNC
is 0x060, the CONVST pulse will lag the PWMSYNC pulse by a
quarter of the ADC update period, or 7.68 µs, with a 12.5 MHz
CLKIN. The ability to phase shift the ADC update relative to
the PWMSYNC pulse is available only in single update mode of
the PWM.
It is also possible to operate the ADCs at a faster update rate
than the PWM switching frequency and still maintain synchro-
nism, as illustrated in Figure 9 (c). In this example, the value
written to the ADCDIV registers is three times larger than the
value written to the PWMTM register, so that the ADC update
rate is three times faster than the PWM switching frequency.
Synchronism is maintained by setting Bits 7 and 8 of the
ADCCTRL register. In addition, it is possible to introduce a
PWMSYNC
PWMSYNC
PWMSYNC
PWMSYNC
CONVST
CONVST
CONVST
CONVST
AH
AH
AH
AH
T
OFFSET
T
T
OFFSET
OFFSET
PWMTM/3
=
(128 − ADCSYNC )
PWMTM/3
128
PWMCHA
PWMCHA
PWMCHA
PWMCHA
PWMTM
PWMTM
PWMTM
PWMTM



ADCDIVn
f
CLKIN



OFFSET
(a)
(b)
(c)
(d)
,
phase shift between the ADC update and PWMSYNC pulses
while operating at different frequencies, as illustrated by Figure 9
(d). The offset is defined by the ADCSYNC register as a fraction
of the ADC update period in an identical manner to before.
ADC Transfer Characteristics
Each ADC converter of the ADMC300 consists of an input
modulator stage and a decimation filter stage that produces the
final conversion result. The output of the decimation filters are
16-bit, left-aligned, two’s complement representation of the
input signal, V
both single-ended and differential modes are shown in Figure
10. The transfer characteristics of the ADC when operated in
the differential configuration are shown in Figure 10 (a) and for
the single-ended configuration in Figure 10 (b). The peak-peak
input voltage is 4 V.
The output code of the ADCs is typically given by:
V
V
REF
REF
= 2.5 V
= 2.5 V
3.5 V
4.5 V
1.5V
0.5V
0xAD30
0xAD30
ANALOG
ANALOG
ADCx = 10,600 ×
INPUT
INPUT
IN
. The ideal ADC transfer characteristics for



ADC CODE
ADC CODE
0x0000
0x0000
V
(a)
(b)
REFIN
2.5
V1
V1

 Vx −VxN

(
ADMC300
V1N
0x52D0
0x52D0
V1N
)