AT40Kxx ATMEL Corporation, AT40Kxx Datasheet
AT40Kxx
Related parts for AT40Kxx
AT40Kxx Summary of contents
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Features • Ultra High Performance – System Speeds to 100 MHz – Array Multipliers > 50 MHz – Flexible SRAM – Internal Tri-state Capability in Each Cell ™ • FreeRAM – Flexible, Single/Dual Port, Synchronous/Asynchronous 10 ns SRAM ...
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Table 1. AT40K/AT40KLV Family Note: Description The AT40K/AT40KLV is a family of fully PCI-compliant, SRAM-based FPGAs with dis- tributed 10 ns programmable synchronous/asynchronous, dual-port/single-port SRAM, 8 global clocks, Cache Logic ability (partially or fully reconfigurable without loss of data), automatic ...
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Cache Logic Design The AT40K/AT40KLV, AT6000 and FPSLIC families are capable of implementing Cache Logic (dynamic full/partial logic reconfiguration, without loss of data, on-the-fly) for building adaptive logic and systems. As new logic functions are required, they can be loaded ...
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The Symmetrical At the heart of the Atmel architecture is a symmetrical array of identical cells, see Figure 1. The array is continuous from one edge to the other, except for bus repeat- Array ers spaced every four cells, see ...
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Figure 2. Floor Plan (Representative Portion) Note: 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA = Vertical Repeater RV = Horizontal Repeater RH = Core Cell RAM RAM ...
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The Busing Network Figure 3 on page 7 depicts one of five identical busing planes. Each plane has three bus resources: a local-bus resource (the middle bus) and two express-bus (both sides) resources. Bus resources are connected via repeaters. Each ...
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Figure 3. Busing Plane (One of Five) 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA = AT40K/AT40KLV Core Cell = Local/Local or Express/Express Turn Point = Row Repeater = Column Repeater Express Express Bus Bus Local Bus 7 ...
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Cell Connections Figure 4(a) depicts direct connections between a cell and its eight nearest neighbors. Figure 4(b) shows the connections between a cell and five horizontal local buses (1 per busing plane) and five vertical local buses (1 per busing ...
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Figure 5. The Cell "1" "1" N "1" 8X1 LUT 8X1 LUT OUT OUT "0" "1" CLOCK RESET/SET ...
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Figure 6. Some Single Cell Modes CARRY AT40K/AT40KLV Series FPGA 10 Synthesis Mode. This mode is ...
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RAM dual-ported RAM blocks are dispersed throughout the array, see Figure 7. A 4-bit Input Data Bus connects to four horizontal local buses distributed over four sector rows (plane 1). A 4-bit Output Data Bus connects to ...
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Reading and writing of the dual-port FreeRAM are independent of each other. Reading the dual-port RAM is completely asynchronous. Latches are transparent; when Load is logic 1, data flows through; when Load ...
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WE 2-to-4 Decoder Write Address Din(0) Din(1) Din(2) Din(3) Din Dout Ain Aout WEN OEN Din(4) Din(5) Din(6) Din(7) Din Dout Ain Aout WEN OEN Din Dout Din Dout Aout Ain Ain Aout WEN WEN OEN OEN Din Dout Din ...
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Clocking Scheme There are eight Global Clock buses (GCK1 - GCK8) on the AT40K/AT40KLV FPGA. Each of the eight dedicated Global Clock buses is connected to one of the dual-use Glo- bal Clock pins. Any clocks used in the design ...
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Figure 10. Clocking (for One Column of Cells) 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA Express Bus (Plane 4; Half Length at Edge) Repeater } FCK (2 per Edge Column of the Array) GCK1 - GCK8 Column Clock Mux “1” ...
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Set/Reset Scheme The AT40K/AT40KLV family reset scheme is essentially the same as the clock scheme except that there is only one Global Reset. A dedicated Global Set/Reset bus can be driven by any User I/O, except those used for clocking ...
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Figure 11. Set/Reset (for One Column of Cells) (Plane 5; Half Length at Edge) 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA Repeater “1” “1” Express Bus “1” “1” Any User I/O can Drive Global Set/Reset Lone Each Cell has a Programmable Set or ...
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I/O Structure PAD The I/O pad is the one that connects the I/O to the outside world. Note that not all I/Os have pads: the ones without pads are called Unbonded I/Os. The number of unbonded I/Os varies with the ...
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Primary, Secondary and The AT40K/AT40KLV has three kinds of I/Os: Primary I/O, Secondary I/O and a Corner I/O. Every edge cell except corner cells on the AT40K/AT40KLV has access to one Pri- Corner I/Os mary I/O and two Secondary I/Os. ...
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Figure 12. West I/O (Mirrored for East I/O) AT40K/AT40KLV AT40K/AT40KLV Series FPGA 20 “0” “1” “0” PULL-UP “1” PAD PULL-DOWN (a) Primary I/O “0” “1” “0” PULL-UP “1” PAD PULL-DOWN (b) Secondary I/O CELL CELL CELL CELL CELL 0896C–FPGA–04/02 ...
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Figure 13. South I/O (Mirrored for North I/O) AT40K/AT40KLV 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA (a) Primary I/O (a) Secondary I/O 21 ...
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Figure 14. Northwest Corner (Similar for NE/SE/SW Corners) AT40K/AT40KLV PULL-DOWN AT40K/AT40KLV Series FPGA 22 PAD VCC TTL/CMOS DRIVE SCHMITT TRI-STATE DELAY “0” “1” “0” PULL-UP “1” PAD PAD GND VCC GND TTL/CMOS DRIVE SCHMITT TRI-STATE DELAY CELL CELL CELL 0896C–FPGA–04/02 ...
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Absolute Maximum Ratings – 5V Commercial/Industrial* AT40K Operating Temperature.................................. -55°C to +125 °C Storage Temperature ..................................... -65 °C to +150°C Voltage on Any Pin with Respect to Ground .................................-0. Supply Voltage (V ) .........................................-0.5V to +7.0V CC Maximum ...
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DC Characteristics – 5V Operation Commercial/Industrial/Military AT40K Symbol Parameter V High-level Input Voltage IH V Low-level Input Voltage IL V High-level Output Voltage OH V Low-level Output Voltage OL I High-level Input Current IH I Low-level Input Current IL High-level ...
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AC Timing Characteristics – 5V Operation AT40K Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Maximum delays are the average of t ...
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AC Timing Characteristics – 5V Operation AT40K Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Maximum delays are the average of t ...
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AC Timing Characteristics – 5V Operation AT40K Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Maximum delays are the average of t ...
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AC Timing Characteristics – 5V Operation AT40K Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Maximum delays are the average of t ...
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FreeRAM Asynchronous Timing Characteristics Single-port Write/Read Dual-port Write with Read Dual-port Read 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA WE t AWS 0 ADDR OXZ DS DATA WE t AWS 0 WR ADDR PREV. WR DATA RD ADDR = WR ...
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FreeRAM Synchronous Timing Characteristics Single-port Write/Read Dual-port Write with Read Dual-port Read AT40K/AT40KLV Series FPGA 30 CLK t WCS WE t ACS 0 ADDR OE t OXZ t DCS DATA CLK t WCS WE t ACS 0 WR ADDR t ...
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Absolute Maximum Ratings – 3.3V Commercial/Industrial* AT40KLV Operating Temperature.................................. -55°C to +125 °C Storage Temperature ..................................... -65 °C to +150°C Voltage on Any Pin with Respect to Ground .................................-0. Supply Voltage (V ) .........................................-0.5V to +7.0V CC Maximum ...
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DC Characteristics – 3.3V Operation Commercial/Industrial AT40KLV Symbol Parameter V High-level Input Voltage IH V Low-level Input Voltage IL V High-level Output Voltage OH V Low-level Output Voltage OL I High-level Input Current IH I Low-level Input Current IL High-level ...
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AC Timing Characteristics – 3.3V Operation AT40KLV Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Maximum delays are the average of t ...
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AC Timing Characteristics – 3.3V Operation AT40KLV Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Maximum delays are the average of t ...
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AC Timing Characteristics – 3.3V Operation AT40KLV Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Maximum delays are the average of t ...
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AC Timing Characteristics – 3.3V Operation AT40KLV Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Cell Function Parameter Async RAM Write t ...
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AT40K05 AT40K10 AT40K20 AT40K05LV AT40K10LV AT40K20LV 128 I/O 192 I/O 256 I/O GND GND GND I/O1, I/O1, I/O1, GCK1 GCK1 GCK1 (A16) (A16) (A16) I/O2 I/O2 I/O2 (A17) (A17) (A17) I/O3 I/O3 I/O3 I/O4 I/O4 I/O4 I/O5 I/O5 I/O5 (A18) ...
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AT40K05 AT40K10 AT40K20 AT40K05LV AT40K10LV AT40K20LV AT40K40LV 128 I/O 192 I/O 256 I/O I/O11 I/O15 I/O19 (A20) (A20) (A20) I/O12 I/O16 I/O20 (A21) (A21) (A21) VCC VCC I/O17 I/O21 I/O18 I/O22 I/O23 I/O24 GND I/O25 I/O26 I/O19 I/O27 I/O20 I/O28 ...
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AT40K05 AT40K10 AT40K20 AT40K05LV AT40K10LV AT40K20LV 128 I/O 192 I/O 256 I/O I/O20 I/O28 I/O36 I/O29 I/O37 I/O30 I/O38 I/O39 I/O40 GND I/O41 I/O42 I/O31 I/O43 I/O32 I/O44 VCC VCC I/O21 I/O33 I/O45 I/O22 I/O34 I/O46 I/O23 I/O35 I/O47 I/O24, ...
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AT40K05 AT40K10 AT40K20 AT40K05LV AT40K10LV AT40K20LV AT40K40LV 128 I/O 192 I/O 256 I/O I/O25 I/O41 I/O55 I/O26 I/O42 I/O56 GND VCC I/O57 I/O58 I/O27 I/O43 I/O59 I/O28 I/O44 I/O60 I/O29 I/O45 I/O61 I/O30 I/O46 I/O62 I/O31 I/O47 I/O63 (3) (3) ...
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AT40K20 AT40K05 AT40K10 AT40K05LV AT40K10LV AT40K20LV 128 I/O 192 I/O 256 I/O I/O38 I/O54 I/O70 (LDC) (LDC) (LDC) I/O71 I/O72 VCC GND I/O39 I/O55 I/O73 I/O40 I/O56 I/O74 I/O57 I/O75 I/O58 I/O76 I/O77 I/O78 I/O59 I/O79 I/O60 I/O80 GND GND ...
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AT40K20 AT40K05 AT40K10 AT40K05LV AT40K10LV AT40K20LV AT40K40LV 128 I/O 192 I/O 256 I/O I/O87 I/O88 GND I/O89 I/O90 I/O67 I/O91 I/O68 I/O92 I/O45 I/O69 I/O93 I/O46 I/O70 I/O94 I/O47 I/O71 I/O95 (D15) (D15) (D15) I/O48 I/O72 I/O96 (INIT) (INIT) (INIT) ...
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AT40K20 AT40K05 AT40K10 AT40K05LV AT40K10LV AT40K20LV 128 I/O 192 I/O 256 I/O I/O106 I/O79 I/O107 I/O80 I/O108 VCC VCC I/O53 I/O81 I/O109 (D12) (D12) (D12) I/O54 I/O82 I/O110 (D11) (D11) (D11) I/O55 I/O83 I/O111 I/O56 I/O84 I/O112 GND GND GND ...
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AT40K20 AT40K05 AT40K10 AT40K05LV AT40K10LV AT40K20LV AT40K40LV 128 I/O 192 I/O 256 I/O I/O61 I/O93 I/O125 I/O62 I/O94 I/O126 I/O63 I/O95 I/O127 (D8) (D8) (D8) I/O64, I/O96, I/O128, GCK4 GCK4 GCK4 GND GND GND CON CON CON Notes: 1. Pads ...
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AT40K20 AT40K05 AT40K10 AT40K05LV AT40K10LV AT40K20LV 128 I/O 192 I/O 256 I/O I/O70 I/O104 I/O138 I/O71 I/O105 I/O139 I/O72 I/O106 I/O140 I/O107 I/O141 I/O108 I/O142 I/O143 I/O144 GND GND GND I/O109 I/O145 I/O110 I/O146 I/O73, I/O111, I/O147, FCK3 FCK3 FCK3 ...
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AT40K20 AT40K05 AT40K10 AT40K05LV AT40K10LV AT40K20LV AT40K40LV 128 I/O 192 I/O 256 I/O I/O77 I/O117 I/O157 I/O78 I/O118 I/O158 I/O79(D4) I/O119(D4) I/O159(D4) I/O80 I/O120 I/O160 VCC VCC VCC GND GND GND I/O81 I/O121 I/O161 (D3) (D3) (D3) I/O82 I/O122 I/O162 ...
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AT40K20 AT40K05 AT40K10 AT40K05LV AT40K10LV AT40K20LV 128 I/O 192 I/O 256 I/O I/O88, I/O130, I/O174, FCK4 FCK4 FCK4 I/O131 I/O175 I/O132 I/O176 GND GND GND I/O177 I/O178 I/O133 I/O179 I/O134 I/O180 I/O135 I/O181 I/O136 I/O182 I/O89 I/O137 I/O183 I/O90 I/O138 ...
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AT40K20 AT40K05 AT40K10 AT40K05LV AT40K10LV AT40K20LV AT40K40LV 128 I/O 192 I/O 256 I/O CCLK CCLK CCLK VCC VCC VCC TSTCLK TSTCLK TSTCLK Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. ...
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AT40K20 AT40K05 AT40K10 AT40K05LV AT40K10LV AT40K20LV 128 I/O 192 I/O 256 I/O I/O155 I/O205 I/O156 I/O206 I/O207 I/O208 GND GND GND I/O105 I/O157 I/O209 I/O106 I/O158 I/O210 I/O159 I/O211 I/O160 I/O212 VCC VCC I/O213 I/O214 I/O215 I/O216 GND I/O107 I/O161 ...
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AT40K20 AT40K05 AT40K10 AT40K05LV AT40K10LV AT40K20LV AT40K40LV 128 I/O 192 I/O 256 I/O I/O112 I/O168 I/O224 (A7) (A7) (A7) GND GND GND VCC VCC VCC I/O113 I/O169 I/O225 (A8) (A8) (A8) I/O114 I/O170 I/O226 (A9) (A9) (A9) I/O115 I/O171 I/O227 ...
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AT40K20 AT40K05 AT40K10 AT40K05LV AT40K10LV AT40K20LV 128 I/O 192 I/O 256 I/O I/O242 I/O181 I/O243 I/O182 I/O244 I/O121 I/O183 I/O245 I/O122 I/O184 I/O246 I/O123 I/O185 I/O247 (A12) (A12) (A12) I/O124 I/O186 I/O248 (A13) (A13) (A13) GND VCC I/O249 I/O250 I/O187 ...
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Power and Ground Pinouts for 352 SBGA A10 A17 G23 H4 U26 W23 AE25 AF10 A1 A2 A25 A26 H26 N1 AE1 AE26 AF19 AF22 Note SBGA packages, Power and Ground pins do not connect directly to die. ...
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Part/Package Availability and User I/O Counts (including Dual-function Pins) (1) Package AT40K05/AT40K05LV 84 PLCC 100 PQFP 100 TQFP 144 LQFP 160 PQFP 208 PQFP 240 PQFP 304 PQFP 352 SBGA Note: 1. Devices in same package are pin-to-pin compatible. 84J ...
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AT40K05/AT40K05LV Ordering Information Usable Gates Operating Voltage 5,000 - 10,000 5.0V 5,000 - 10,000 5.0V 5,000 - 10,000 3.3V 5,000 - 10,000 3.3V Note: 1. For military parts, contact Atmel at fpga@atmel.com. AT40K/AT40KLV Series FPGA 54 Speed Grade (ns) Ordering ...
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AT40K10/AT40K10LV Ordering Information Usable Gates Operating Voltage 10,000 - 20,000 5.0V 10,000 - 20,000 5.0V 10,000 - 20,000 3.3V 10,000 - 20,000 3.3V Note: 1. For military parts, contact Atmel at fpga@atmel.com. 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA Speed Grade (ns) Ordering ...
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AT40K20/AT40K20LV Ordering Information Usable Gates Operating Voltage 20,000 - 30,000 5.0V 20,000 - 30,000 5.0V 20,000 - 30,000 3.3V 20,000 - 30,000 3.3V Note: 1. For military parts, contact Atmel at fpga@atmel.com AT40K/AT40KLV Series FPGA 56 Speed Grade (ns) Ordering ...
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AT40K40/AT40K40LV Ordering Information Usable Gates Operating Voltage 40,000 - 50,000 5.0V 40,000 - 50,000 5.0V 40,000 - 50,000 3.3V 40,000 - 50,000 3.3V Note: 1. For military parts, contact Atmel at fpga@atmel.com. 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA Speed Grade (ns) Ordering ...
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Packaging Information 84J – PLCC 1.14(0.045) X 45˚ 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AF. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) ...
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TQFP Top View Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. The top package body ...
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PQFP E1 Top View Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MS-022, Variation GC-1, for additional information determined at seating plane. 3. Regardless of ...
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LQFP Top View Side View 1. This drawing is for general information only; refer to JEDEC Drawing MS-026 for additional information. Notes: 2. The top package body size may be smaller than ...
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PQFP D1 E1 Top View Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MS-022, Variation DD-1, for additional information determined at seating plane. 3. Regardless ...
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TQFP e Top View Bottom View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. The top package body size may be smaller than ...
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PQFP D1 E1 Top View Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MS-029, Variation GA, for additional information. 2. All dimensioning and tolerancing conforms to ASME Y14.5M-1994. ...
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PQFP D1 E1 Top View Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MS-029, Variation JA, for additional information. 2. All dimensioning and tolerancing conforms to ASME Y14.5M-1994. ...
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SBGA A1 BALL CORNER D A1 BALL I.D. E Top View Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-192, Variation BAR-2, for additional information. 2. JEDEC variations ...
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... Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...