XC73144-10 Xilinx, XC73144-10 Datasheet - Page 3

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XC73144-10

Manufacturer Part Number
XC73144-10
Description
144-Macrocell CMOS EPLD
Manufacturer
Xilinx
Datasheet

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XC73144 CMOS EPLD
Absolute Maximum Ratings
Warning : Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings condi-
tions for extended periods of time may affect device reliability.
Recommended Operating Conditions
Power Management
The XC73144 features a power-management scheme
which permits non-speed-critical paths of a design to be
operated at reduced power. Overall power dissipation is
often reduced significantly, since, in most systems only a
few paths are speed critical.
Macrocells can individually be specified for high per-
formance or low power operation by adding attributes to
the logic schematic, or declaration statements to the
behavioral description. To minimize power dissipation,
unused Function Blocks are turned off and unused
Macrocells in used Function Blocks are configured for low
power operation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
Where:
Symbol
V
V
V
V
V
V
T
Symbol
V
V
V
T
T
IN
CCINT
CCIO
CCIO
IL
IH
O
MC
MC
MC
f
I
CC
STG
SOL
CC
IN
TS
MC (0.015 mA/MHz) f
(mA) = MC
HP
LP
/
= Macrocells in high-performance mode
= Macrocells in low-power mode
= Total number of Macrocells used
= Clock frequency (MHz)
Parameter
Supply voltage relative to GND
Supply voltage relative to GND
Supply voltage relative to GND
I/O supply voltage relative to GND
Low-level input voltage
High-level input voltage
Output voltage
Input signal transition time
Parameter
Supply voltage with respect to GND
DC Input voltage with respect to GND
Voltage applied to 3-state output with respect to GND
Storage temperature
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)
HP
(2.4) + MC
LP
(2.1) +
Commercial
Industrial
Military
2-67
T
A
= -55
Figure 2 shows a typical calculation for the XC73144 device,
programmed as eight 16-bit counters and operating at the
indicated clock frequency.
Figure 2. Typical I
T
o
A
C to T
T
= -40
A
500
400
300
200
100
= 0
0
C
o
o
C to 70
C to 85
= +125
CC
o
o
o
C
C
C
vs Frequency for XC73144
Clock Frequency (MHz)
Min
4.75
4.5
4.5
0
2.0
0
3.0
-0.5 to V
-0.5 to V
-65 to +150
-0.5 to 7.0
Value
50
+260
CC
CC
V
+0.5
+0.5
Max
CC
V
5.25
5.5
5.5
3.6
0.8
50.0
CCIO
+0.5
Units
V
V
Units
V
C
C
100
X5768
ns
V
V
V
V
V
V
V

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