MT3170 MITEL [Mitel Networks Corporation], MT3170 Datasheet - Page 2

• Manufacturer Part Number: MT3170
• Description: Wide Dynamic Range DTMF Receiver
• Manufacturer: MITEL [Mitel Networks Corporation]

MT3170B/71B, MT3270B/71B, MT3370B/71B
4-4
Pin Description
PWDN
INPUT
1,5,7,8,
10, 12,
337xB
14,16,
VSS
CLK
11
13
15
18
17
2
4
6
9
3
MT3170B/71B
1
2
3
4
327xB
Pin #
8
7
6
5
1
2
3
4
5
6
7
8
-
-
8 PIN PLASTIC DIP
VDD
ACK
SD
ESt/
DStD
317xB
INPUT
OSC2
OSC1
VSS
1
3
4
5
6
7
8
2
-
-
MT3270B/71B
1
2
3
4
(MT3x70B)
(MT3x71B)
PWDN
INPUT
Name
OSC2
OSC1
(CLK)
DStD
ACK
V
ESt
V
SD
NC
SS
DD
8
7
6
5
VDD
ESt/
DStD
ACK
SD
Figure 2 - Pin Connections
DTMF/CP Input. Input signal must be AC coupled via capacitor.
Oscillator Output.
Oscillator/Clock Input. This pin can either be driven by:
1)
2)
Ground. (0V)
Serial Data/Call Progress Output. This pin serves the dual function
of being the serial data output when clock pulses are applied after
validation of DTMF signal, and also indicates the cadence of call
progress input. As DTMF signal lies in the same frequency band as
call progress signal, this pin may toggle for DTMF input. The SD pin
is at logic low in powerdown state.
Acknowledge Pulse Input. After ESt or DStD is high, applying a
sequence of four pulses on this pin will then shift out four bits on the
SD pin, representing the decoded DTMF digit. The rising edge of the
first clock is used to latch the 4-bit data prior to shifting. This pin is
pulled down internally. The idle state of the ACK signal should be
low.
Early Steering Output. A logic high on ESt indicates that a DTMF
signal is present. ESt is at logic low in powerdown state.
Delayed Steering Output. A logic high on DStD indicates that a
valid DTMF digit has been detected. DStD is at logic low in
powerdown state.
Positive Power Supply (5V Typ.) Performance of the device can be
optimized by minimizing noise on the supply rails. Decoupling
capacitors across V
No Connection. Pin is unconnected internally.
Power Down Input. A logic high on this pin will power down the
device to reduce power consumption. This pin is pulled down
internally and can be left open if not used. ACK pin should be at logic
’0’ to power down device.
an external digital clock with defined input logic levels. OSC2
connecting a crystal or ceramic resonator between OSC1 and
PWDN
INPUT
should be left open.
OSC2 pins.
OSC2
OSC1
VSS
NC
NC
NC
NC
18 PIN PLASTIC SOIC
MT3370B/71B
1
2
3
4
5
6
7
8
9
DD
18
17
16
15
14
13
12
11
10
and V
VDD
NC
NC
ESt/DStD
NC
ACK
NC
SD
NC
Description
SS
are therefore recommended.
PWDN
INPUT
OSC2
OSC1
VSS
NC
NC
NC
NC
NC
10
MT3370B/71B
1
2
3
4
5
6
7
8
9
20 PIN SSOP
20
19
18
17
16
15
14
13
12
11
NC
NC
VDD
NC
ESt/DStD
NC
ACK
SD
NC
NC