CY7C024-25JI CYPRESS [Cypress Semiconductor], CY7C024-25JI Datasheet

CY7C024-25JI

Manufacturer Part Number

CY7C024-25JI

Description

4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY

Manufacturer

CYPRESS [Cypress Semiconductor]

Datasheet

1.CY7C024-25JI.pdf (20 pages)

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Cypress Semiconductor Corporation

Document #: 38-06035 Rev. *B

Features

Logic Block Diagram

• True Dual-Ported memory cells which allow

• 4K x 16 organization (CY7C024)

• 4K x 18 organization (CY7C0241)

• 8K x 16 organization (CY7C025)

• 8K x 18 organization (CY7C0251)

• 0.65-micron CMOS for optimum speed/power

• High-speed access: 15 ns

• Low operating power: I

• Fully asynchronous operation

• Automatic power-down

• Expandable data bus to 32/36 bits or more using

• On-chip arbitration logic

• Semaphores included to permit software handshaking

• INT flag for port-to-port communication

• Separate upper-byte and lower-byte control

• Pin select for Master or Slave

• Available in 84-pin PLCC and 100-pin TQFP

simultaneous reads of the same memory location

Master/Slave chip select when using more than one

device

between ports

(CY7C025/0251)

= 150 mA (typ.)

I/O

R/W

– I/O

BUSY

15L

[2]

[3]

[1]

12L

11L

R/W

•

SEM

INT

3901 North First Street

4K x 16/18 and 8K x 16/18 Dual-Port

ADDRESS

DECODER

CONTROL

Static RAM with SEM, INT, BUSY

I/O

Functional Description

The CY7C024/0241 and CY7C025/0251 are low-power

CMOS 4K x 16/18 and 8K x 16/18 dual-port static RAMs. Var-

ious arbitration schemes are included on the CY7C024/0241

and CY7C025/0251 to handle situations when multiple pro-

cessors access the same piece of data. Two ports are provid-

ed, permitting independent, asynchronous access for reads

and writes to any location in memory. The CY7C024/0241 and

CY7C025/0251 can be utilized as standalone 16-/18-bit du-

al-port static RAMs or multiple devices can be combined in

order to function as a 32-/36-bit or wider master/slave du-

al-port static RAM. An M/S pin is provided for implementing

32-/36-bit or wider memory applications without the need for

separate master and slave devices or additional discrete logic.

Application areas include interprocessor/multiprocessor de-

signs, communications status buffering, and dual-port vid-

eo/graphics memory.

Each port has independent control pins: Chip Enable (CE),

Read or Write Enable (R/W), and Output Enable (OE). Two flags

are provided on each port (BUSY and INT). BUSY signals that the

port is trying to access the same location currently being accessed by

the other port. The Interrupt Flag (INT) permits communication be-

tween ports or systems by means of a mail box. The semaphores are

used to pass a flag, or token, from one port to the other to indicate that

a shared resource is in use. The semaphore logic is comprised of

eight shared latches. Only one side can control the latch (semaphore)

at any time. Control of a semaphore indicates that a shared resource

is in use. An automatic power-down feature is controlled indepen-

dently on each port by a chip select (CE) pin.

The CY7C024/0241 and CY7C025/0251 are available in

84-pin PLCCs (CY7C024 and CY7C025 only) and 100-pin

Thin Quad Plastic Flatpack (TQFP).

ARBITRATION

SEMAPHORE

INTERRUPT

MEMORY

ARRAY

M/S

•

San Jose

CONTROL

I/O

ADDRESS

DECODER

•

CA 95134

INT

SEM

R/W

CY7C024/0241

CY7C025/0251

I/O

BUSY

12R

11R

Revised June 22, 2004

R/W

–

(CY7C025/0251)

–

I/O

[1]

•

15R

[3]

[2]

7C024–1

408-943-2600

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