IS61/64WV20488BLL ISSI [Integrated Silicon Solution, Inc], IS61/64WV20488BLL Datasheet - Page 14

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IS61/64WV20488BLL

Manufacturer Part Number
IS61/64WV20488BLL
Description
2M x 8 HIGH-SPEED CMOS STATIC RAM
Manufacturer
ISSI [Integrated Silicon Solution, Inc]
Datasheet
AC WAVEFORMS
WRITE CYCLE NO. 2
IS61WV20488ALL, IS61/64WV20488BLL
14
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
2. I/O will assume the High-Z state if OE > V
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
ADDRESS
D
OUT
WE
D
OE
CE
IN
LOW
t
SA
(1,2)
DATA UNDEFINED
(WE Controlled: OE is HIGH During Write Cycle)
Ih
.
Integrated Silicon Solution, Inc. — www.issi.com —
VALID ADDRESS
t
t
AW
HZWE
t
t
PWE1
WC
HIGH-Z
t
SD
DATA
IN
VALID
t
HD
t
LZWE
t
HA
CE_WR2.eps
1-800-379-4774
08/04/2010
Rev. B

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