ICS91305YGILF-T ICSI [Integrated Circuit Solution Inc], ICS91305YGILF-T Datasheet

ICS91305YGILF-T

Manufacturer Part Number

ICS91305YGILF-T

Description

High Performance Communication Buffer

Manufacturer

ICSI [Integrated Circuit Solution Inc]

Datasheet

1.ICS91305YGILF-T.pdf (8 pages)

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General Description

Pin Configuration

0691F—06/03/05

High Performance Communication Buffer

The ICS91305I is a high performance, low skew, low jitter

clock driver. It uses a phase lock loop (PLL) technology

to align, in both phase and frequency, the REF input with

the CLKOUT signal. It is designed to distribute high speed

clocks in communication systems operating at speeds

from 10 to 133 MHz.

ICS91305I is a zero delay buffer that provides

synchronization between the input and output. The

synchronization is established via CLKOUT feed back to

the input of the PLL. Since the skew between the input and

output is less than +/- 350 pS, the part acts as a zero delay

buffer.

The ICS91305I comes in an eight pin 150 mil SOIC

package. It has five output clocks. In the absence of REF

input, will be in the power down mode. In this mode, the

PLL is turned off and the output buffers are pulled low.

Power down mode provides the lowest power consumption

for a standby condition.

CLK2

CLK1

GND

REF

8 pin SOIC & TSSOP

Integrated

Circuit

Systems, Inc.

CLKOUT

CLK4

VDD

CLK3

Features

•

Block Diagram

Zero input - output delay

Frequency range 10 - 133 MHz (3.3V)

5V tolerant input REF

High loop filter bandwidth ideal for Spread

Spectrum applications.

Less than 200 ps Jitter between outputs

Skew controlled outputs

Skew less than 250 ps between outputs

Available in 8 pin 150 mil SOIC & 173 mil

TSSOP packages

3.3V ±10% operation

Supports industrial temperature range -40°C to

85°C

ICS91305I

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ICS91305YGILF-T Summary of contents

Page 1

Integrated Circuit Systems, Inc. High Performance Communication Buffer General Description The ICS91305I is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input ...

Page 2

ICS91305I Pin Descriptions ...

Page 3

Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs (Except REF ...

Page 4

ICS91305I Switching Characteristics PARAMETER SYMBOL Output period t1 Input period t1 Duty Cycle 1 Dt1 Duty Cycle 1 Dt2 1 Rise Time tr1 Fall Time 1 tf1 Delay, REF Rising Edge to CLKOUT Dr1 1, 2 Rising Edge Output to ...

Page 5

Output to Output Skew The skew between CLKOUT and the CLK(1-4) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all ...

Page 6

ICS91305I N INDE X ARE 150 mil (Narrow Body) SOIC Ordering Information ICS91305yMILF-T Example: ICS XXXX y M LF- T Designation for tape and reel packaging RoHS Compliant (Optional) Package Type Revision ...

Page 7

... INDEX AREA Ordering Information ICS91305yGILF-T Example: ICS XXXX y G LF- T 0691F—06/03/05 c SYMBOL α α aaa VARIATIONS Reference Doc.: JEDEC Publication 95, MO-153 SEATING PLANE 10-0035 aaa C Designation for tape and reel packaging ...

Page 8

ICS91305I Revision History Rev. Issue Date Description 1. Resized Electrical Characteristics Table. F 6/3/2005 2. Updated LF Ordering Information from "Lead Free" to "RoHS Compliant". 0691F—06/03/05 8 Page # 3,6,7 ...

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