CAT28F020 CATALYST [Catalyst Semiconductor], CAT28F020 Datasheet

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CAT28F020

Manufacturer Part Number
CAT28F020
Description
2 Megabit CMOS Flash Memory
Manufacturer
CATALYST [Catalyst Semiconductor]
Datasheet

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CAT28F020
2 Megabit CMOS Flash Memory
FEATURES
DESCRIPTION
The CAT28F020 is a high speed 256K x 8-bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after-sale
code updates. Electrical erasure of the full memory
contents is achieved typically within 0.5 second.
It is pin and Read timing compatible with standard
EPROM and E
Erase are performed through an operation and verify
algorithm. The instructions are input via the I/O bus,
BLOCK DIAGRAM
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Fast Read Access Time: 70/90/120 ns
Low Power CMOS Dissipation:
– Active: 30 mA max (CMOS/TTL levels)
– Standby: 1 mA max (TTL levels)
– Standby: 100 A max (CMOS levels)
High Speed Programming:
– 10 s per byte
– 4 Seconds Typical Chip Program
0.5 Seconds Typical Chip-Erase
12.0V
A 0 –A 17
5% Programming and Erase Voltage
WE
CE
OE
2
PROM devices.
VOLTAGE VERIFY
SWITCH
COMMAND
REGISTER
Programming and
PROGRAM VOLTAGE
ERASE VOLTAGE
SWITCH
SWITCH
Y-DECODER
X-DECODER
1
using a two write cycle scheme. Address and Data are
latched to free the I/O bus and address bus during the
write operation.
The CAT28F020 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 32-pin plastic DIP, 32-pin PLCC or 32-pin
TSOP packages.
Commercial, Industrial and Automotive
Temperature Ranges
Stop Timer for Program/Erase
On-Chip Address and Data Latches
JEDEC Standard Pinouts:
– 32-pin DIP
– 32-pin PLCC
– 32-pin TSOP (8 x 20)
100,000 Program/Erase Cycles
10 Year Data Retention
Electronic Signature
CE, OE LOGIC
LATCH
DATA
I/O BUFFERS
2,097,152 BIT
I/O 0 –I/O 7
Y-GATING
second source
MEMORY
Licensed Intel
ARRAY
SENSE
AMP
Doc. No. 25037-00 2/98 F-1
5115 FHD F02

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CAT28F020 Summary of contents

Page 1

... Seconds Typical Chip Program 0.5 Seconds Typical Chip-Erase 12.0V 5% Programming and Erase Voltage DESCRIPTION The CAT28F020 is a high speed 256K x 8-bit electrically erasable and reprogrammable Flash memory ideally suited for applications requiring in-system or after-sale code updates. Electrical erasure of the full memory contents is achieved typically within 0.5 second. ...

Page 2

... CAT28F020 PIN CONFIGURATION DIP Package ( ...

Page 3

... Units 100K Cycles/Byte 10 Years 2000 Volts 100 mA Limits Min Max 2.0V for periods of less than 20ns CAT28F020 Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 Units Conditions OUT +1V ...

Page 4

... CAT28F020 D.C. OPERATING CHARACTERISTICS V = +5V 10%, unless otherwise specified. CC Symbol Parameter I Input Leakage Current LI I Output Leakage Current Standby Current CMOS SB1 Standby Current TTL SB2 Active Read Current CC1 CC ( Programming Current CC2 CC ( Erase Current CC3 ...

Page 5

... Min. Max (3)(4)(5) Figure 2. Highspeed A.C. Testing Input/Output 3.0 V REFERENCE POINTS INPUT PULSE LEVELS 0.0 V Testing Load Circuit (example) DEVICE UNDER TEST 5 CAT28F020 Limits Max. Unit 4.5 5.5 0 6.5 12.6 (7) (7) 28F020-12 Min. Max. Min. Max. Unit 90 120 ns 90 120 ns 90 120 ...

Page 6

... CAT28F020 A.C. CHARACTERISTICS, Program/Erase Operation V = +5V 10%, unless otherwise specified. CC JEDEC Standard Symbol Symbol Parameter t t Write Cycle Time AVAV Address Setup Time AVWL Address Hold Time WLAX Data Setup Time DVWH Data Hold Time WHDX Setup Time ...

Page 7

... Read X 90H Read X 20H Write A A0H Read IN X 40H Write X C0H Read X FFH Write , PPL PPH 7 CAT28F020 I/O Notes D OUT High-Z High-Z 31H 12V BDH 12V See Command Table IN D During Write Cycle IN D During Write Cycle ...

Page 8

... A Read cycle from address 0001H retrieves the binary code for the device on outputs I/O 28F020 Code = 1011 1101 (BDH) Standby Mode With logic-high level, the CAT28F020 is placed in a standby mode where most of the device circuitry is disabled, thereby substantially reducing power con- sumption. The outputs are placed in a high-impedance ...

Page 9

... ERASE VERIFY COMMAND COMMAND WHWH2 DATA IN DATA IN = 20H = A0H 9 CAT28F020 to I ERASE V CC POWER-DOWN/ VERIFICATION STANDBY EHQZ WHGL OLZ VALID t LZ DATA OUT ...

Page 10

... CAT28F020 (1) Figure 5. Chip Erase Algorithm START ERASURE APPLY V PPH PROGRAM ALL BYTES TO 00H INITIALIZE ADDRESS INITIALIZE PLSCNT = 0 WRITE ERASE SETUP COMMAND WRITE ERASE COMMAND TIME OUT 10ms WRITE ERASE VERIFY COMMAND TIME OUT 6 s INCREMENT ADDRESS READ DATA FROM DEVICE DATA = ...

Page 11

... PROGRAM & DATA VERIFY PROGRAMMING COMMAND WHWH1 DATA IN 11 CAT28F020 . Refer to AC Characteristics (Program/ CC PROGRAM V CC POWER-DOWN/ VERIFICATION STANDBY EHQZ WHGL OLZ DATA IN = C0H VALID ...

Page 12

... CAT28F020 Figure 7. Programming Algorithm START PROGRAMMING APPLY V PPH INITIALIZE ADDRESS PLSCNT = 0 WRITE SETUP PROG. COMMAND WRITE PROG. CMD ADDR AND DATA TIME OUT 10 s WRITE PROGRAM VERIFY COMMAND TIME OUT 6 s READ DATA FROM DEVICE VERIFY DATA ? YES NO LAST INCREMENT ADDRESS? ...

Page 13

... In other words, V may power up in any order. Additionally V hardwired to V independent of the state of V PPH any power up/down cycling. The internal command register of the CAT28F020 is reset to the Read Mode on power up. Figure 8. Alternate A.C. Timing for Program Operation SETUP PROGRAM V CC POWER-UP COMMAND & ...

Page 14

... Device # CAT 28F020 Product Number Optional Company ID * -40˚ to +125˚ is available upon request. Note: (1) The device used in the above example is a CAT28F020NI-12T (PLCC, Industrial Temperature, 120 ns access time, Tape & Reel). Doc. No. 25037-00 2/98 F-1 28F020-90 28F020-70 Max. Min. Max. Min ...

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