LMH2190TM-38 NSC [National Semiconductor], LMH2190TM-38 Datasheet - Page 16

• Manufacturer Part Number: LMH2190TM-38
• Description: Quad Channel 27 MHz Clock Tree Driver with I2C Interface
• Manufacturer: NSC [National Semiconductor]

www.national.com
edge clock pulse. The receiver must pull down the SDA line
during the 9th clock pulse, signifying an acknowledge. A re-
ceiver which has been addressed must generate an acknowl-
edge after each byte has been received.
After the START condition, the I
dress
an eight bit which is a data direction bit (R/W). For the eighth
bit, a “0” indicates a WRITE and a “1” indicates a READ. The
second byte selects the register to which the data will be writ-
ten. The third byte contains data to write to the selected
register.
(Figure
14). This address is seven bits long followed by
FIGURE 14. I
2
C Chip Address
2
C master sends a chip ad-
FIGURE 15. Example I
FIGURE 16. Example I
30083820
16
Register changes take effect at the SCL rising edge during
the last ACK from slave. An example of a WRITE cycle is
given in
plished, a WRITE function must precede the READ function,
as shown in the Read Cycle waveform
2
2
C Write Cycle
C Read Cycle
Figure
15. When a READ function is to be accom-
(Figure
30083823
16).
30083824