ADF4351BCPZ AD [Analog Devices], ADF4351BCPZ Datasheet - Page 16

• Manufacturer Part Number: ADF4351BCPZ
• Description: Wideband Synthesizer
• Manufacturer: AD [Analog Devices]

ADF4351
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
L2
0
0
1
1
0
M3
0
0
0
0
1
1
1
1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
L1
0
1
0
1
M2
0
0
1
1
0
0
1
1
0
0
NOISE MODE
LOW NOISE MODE
RESERVED
RESERVED
LOW SPUR MODE
NOISE AND
LOW SPUR
M1
0
1
0
1
0
1
0
1
L2
0
MODES
LOW
RESERVED
OUTPUT
THREE-STATE OUTPUT
DV
DGND
R COUNTER OUTPUT
N DIVIDER OUTPUT
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
RESERVED
L1
0
DD
M3
0
MUXOUT
M2
0
F4
0
1
M1
0
BAND SELECT
CLOCK MODE
LOW
HIGH
RD2
0
1
R10
0
0
.
.
.
1
1
1
1
RD2
0
REFERENCE
DOUBLER
DISABLED
ENABLED
RD1
0
1
RD1
R9
F4
0
0
1
1
1
1
.
.
.
REFERENCE DIVIDE-BY-2
DISABLED
ENABLED
R10
...
...
...
...
...
...
...
...
...
...
F3
0
1
F3
R2
0
1
0
0
1
1
.
.
.
ANTIBACKLASH
PULSE WIDTH
6ns (FRAC-N)
3ns (INT-N)
R9
F2
0
1
F2
R1
1
0
0
1
0
1
.
.
.
R8
CHARGE
CANCELATION
DISABLED
ENABLED
0
R COUNTER (R)
1
2
.
.
.
1020
1021
1022
1023
R7
10-BIT R COUNTER
0
F1
0
1
R6
F1
Figure 26. Register 2 (R2)
Figure 27. Register 3 (R3)
CYCLE SLIP
REDUCTION
DISABLED
ENABLED
Rev. 0 | Page 16 of 28
R5
0
C2
0
0
1
1
R4
CP4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
C2
MODE
CLK
C1
0
1
0
1
DIV
D1
0
1
R3
DBR
CP3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C1
DOUBLE BUFFER
R4 [DB22:DB20]
CLOCK DIVIDER MODE
CLOCK DIVIDER OFF
FAST LOCK ENABLE
RESYNC ENABLE
RESERVED
DISABLED
ENABLED
R2
D12
CP2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
R1
D11
D1
CP1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D10
CP4
I CP (mA)
5.1kΩ
0.31
0.63
0.94
1.25
1.56
1.88
2.19
2.50
2.81
3.13
3.44
3.75
4.06
4.38
4.69
5.00
D9
12-BIT CLOCK DIVIDER VALUE
CURRENT
CP3
CHARGE
SETTING
PUMP
D8
CP2
D12
0
0
0
0
.
.
.
1
1
1
1
U6
0
1
D7
U4
0
1
CP1
U5
0
1
D11 ... D2
0
0
0
0
.
.
.
1
1
1
1
LDF
FRAC-N
INT-N
D6
PD POLARITY
NEGATIVE
POSITIVE
... 0
... 0
... 1
... 1
... .
... .
... .
... 0
... 0
... 1
... 1
U6
LDP
10ns
6ns
D5
U5
D4
D1
0
1
0
1
.
.
.
0
1
0
1
U4
D3
U3
CLOCK DIVIDER VALUE
0
1
2
3
.
.
.
4092
4093
4094
4095
U3
0
1
D2
U2
U2
0
1
POWER-DOWN
DISABLED
ENABLED
DB3
Data Sheet
D1
U1
U1
0
1
CP
THREE-STATE
DISABLED
ENABLED
C3(0) C2(1) C1(1)
C3(0) C2(1) C1(0)
DB2
DB2
COUNTER
RESET
DISABLED
ENABLED
CONTROL
CONTROL
BITS
DB1
BITS
DB1
DB0
DB0