CAT9554A ONSEMI [ON Semiconductor], CAT9554A Datasheet

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CAT9554A

Manufacturer Part Number
CAT9554A
Description
Manufacturer
ONSEMI [ON Semiconductor]
Datasheet

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8-bit I²C and SMBus I/O Port with Interrupt
FEATURES
APPLICATIONS
BLOCK DIAGRAM
Notes:
(1) All I/Os are set to inputs at RESET.
© 2008 SCILLC. All rights reserved
Characteristics subject to change without notice
400kHz I²C bus compatible
2.3V to 5.5V operation
Low stand-by current
5V tolerant I/Os
8 I/O pins that default to inputs at power-up
High drive capability
Individual I/O configuration
Polarity inversion register
Active low interrupt output
Internal power-on reset
No glitch on power-up
Noise filter on SDA/SCL inputs
Cascadable up to 8 devices
Industrial temperature range
RoHS-compliant 16-lead SOIC and TSSOP, and
16-pad TQFN (4 x 4mm) packages
White goods (dishwashers, washing machines)
Handheld devices (cell phones, PDAs, digital
cameras)
Data Communications (routers, hubs and
servers)
SDA
SCL
V
V
CC
A0
A1
A2
SS
(1)
FILTER
INPUT
(1)
POWER-ON
RESET
I
CONTROL
2
C/SMBUS
1
WRITE pulse
READ pulse
DESCRIPTION
The CAT9554 and CAT9554A are CMOS devices that
provide 8-bit parallel input/output port expansion for
I²C and SMBus compatible applications. These I/O
expanders provide a simple solution in applications
where additional I/Os are needed: sensors, power
switches, LEDs, pushbuttons, and fans.
The CAT9554/9554A consist of an input port register,
an output port register, a configuration register, a
polarity
compatible serial interface.
Any of the eight I/Os can be configured as an input or
output by writing to the configuration register. The
system master can invert the CAT9554/9554A input
data by writing to the active-high polarity inversion
register.
The CAT9554/9554A features an active low interrupt
output which indicates to the system master that an
input state has changed.
The device’s extended addressing capability allows up
to 8 devices to share the same bus. The CAT9554A is
identical to the CAT9554 except the fixed part of the
I²C slave address is different. This allows up to 16 of
devices (eight CAT9554 and eight CAT9554A) to be
connected on the same bus.
8-BIT
For Ordering Information details, see page 15.
OUTPUT
inversion
PORTS
INPUT/
LP FILTER
CAT9554, CAT9554A
register
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
V
CC
and
INT
an
Doc. No. MD-9002, Rev. F
I²C/SMBus-

Related parts for CAT9554A

CAT9554A Summary of contents

Page 1

... The device’s extended addressing capability allows devices to share the same bus. The CAT9554A is identical to the CAT9554 except the fixed part of the I²C slave address is different. This allows devices (eight CAT9554 and eight CAT9554A connected on the same bus ...

Page 2

... CAT9554, CAT9554A PIN CONFIGURATION SOIC (W), TSSOP ( PIN DESCRIPTION SOIC / TSSOP TQFN 4-7 2 9-12 7- ABSOLUTE MAXIMUM RATINGS Parameters V with Respect to Ground CC Voltage on Any Pin with Respect to Ground ...

Page 3

... CC ( - - 3.6V 5.5V CAT9554, CAT9554A Min Typ Max Unit 2.3 — 5.5 — 104 175 — 550 700 — 0.25 1 — 1.5 1.65 -0.5 — — 5 — — — ...

Page 4

... CAT9554, CAT9554A A.C. CHARACTERISTICS V = 2.3V to 5.5V -40°C to +85°C, unless otherwise specified Symbol Parameter F Clock Frequency SCL t START Condition Hold Time HD:STA t Low Period of SCL Clock LOW t High Period of SCL Clock HIGH t START Condition Setup Time SU:STA t Data In Hold Time HD:DAT ...

Page 5

... Characteristics subject to change without notice ≤ 10ns 0. 0. 0.4V to 2.4V 0.8V, 2.0V 0.5V CC Current Souce I = 3mA Current Source HIGH LOW t LOW t HD:DAT t HD:STA t SU:DAT Figure 1. I²C Serial Interface Timing 5 CAT9554, CAT9554A = 100pF L = 10mA 50pF L t SU:STO t BUF Doc. No. MD-9002, Rev. F ...

Page 6

... CAT9554, CAT9554A PIN DESCRIPTION SCL: Serial Clock The serial clock input clocks all data transferred into or out of the device. The SCL line requires a pull-up resistor driven by an open drain output. SDA: Serial Data/Address The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs ...

Page 7

... Output Port Register Input Port Register D Q LATCH Polarity Inversion Register to I CAT9554, CAT9554A Output Port Register Data 100kΩ I Input Port Register Data To INT Polarity Register Data 7 Doc. No. MD-9002, Rev ...

Page 8

... CAT9554/9554A for a read or write operation. The four most significant bits of the slave address are fixed as binary 0100 for the CAT9554 (Figure 6) and as 0111 for the CAT9554A (Figure 7). The CAT9554/9554A uses the next three bits as address bits. ...

Page 9

... CAT9554, CAT9554A ACKNOWLEDGE After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The SDA line remains stable LOW during the HIGH period of the acknowledge related clock pulse (Figure 5) ...

Page 10

... CAT9554, CAT9554A The output port register sets the outgoing logic levels of the I/O ports, defined as outputs by the configuration register. Bit values in this register have no effect on I/O pins defined as inputs. Reads from the output port register reflect the value that is in the flip-flop controlling the output, not the actual I/O pin value ...

Page 11

... R DATA 1 acknowledge from master DATA 2 DATA Figure 12. Read Input Port Register 11 CAT9554, CAT9554A internal state machine acknowledge from master data from register R DATA first byte no acknowledge from master data from register ...

Page 12

... CAT9554, CAT9554A PACKAGE OUTLINE DRAWINGS (1) (2) SOIC 16-Lead 150mils (W) PIN#1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MS-012 Doc. No. MD-9002 Rev. F SYMBOL MIN A 1.35 A1 0.10 b 0. 9.80 E 5. 0.25 L 0.40 θ ...

Page 13

... Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MO-153. © 2008 SCILLC. All rights reserved Characteristics subject to change without notice SYMBOL θ1 A2 θ CAT9554, CAT9554A MIN NOM MAX 1.10 0.05 0.15 0.85 0.95 0.19 0.30 0.13 0.20 4.90 5.10 6.30 6.50 4.30 4.50 0.65 BSC 1.00 REF 0.45 0.75 0° ...

Page 14

... CAT9554, CAT9554A (1) (2) TQFN 16-Pad 4 x 4mm (HV4) D PIN#1 INDEX AREA TOP VIEW SYMBOL MIN NOM A 0.70 0.75 A1 0.00 0.02 A3 0.20 REF b 0.25 0.30 D 3.90 4.00 D2 2.00 – E 3.90 4.00 E2 2.00 – e 0.65 BSC L 0.45 – Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MO-220. Doc. No. MD-9002 Rev ...

Page 15

... Lead Finish Part Number NiPdAu CAT9554AWI-G NiPdAu CAT9554AWI-GT2 NiPdAu CAT9554AYI-G NiPdAu CAT9554AYI-GT2 NiPdAu CAT9554AHV4I-G NiPdAu CAT9554AHV4I-GT2 15 CAT9554, CAT9554A - G T2 Tape & Reel T: Tape & Reel 2: 2,000/Reel Package Lead Finish SOIC NiPdAu SOIC NiPdAu TSSOP NiPdAu TSSOP NiPdAu TQFN ...

Page 16

... CAT9554, CAT9554A REVISION HISTORY Date Revision Description 08-Jul-05 A Initial Issue 28-Jun-06 B Update Features Add Applications Update Descriptions Update Pin Description Table Update Absolute Maximum Ratings Update D.C. Operating Characteristics Update A.C. Characteristics Update A.C. Test Conditions Update Pin Description Update Figure 2, Figure 4, Figure 5, Figure 8 and Figure 12 ...

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