PCF26100ET PHILIPS [NXP Semiconductors], PCF26100ET Datasheet - Page 10

• Manufacturer Part Number: PCF26100ET
• Description: Bluetooth Adapter IC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Table 3 Adapter timing parameters
6.3.1
The T_GFSK data output has 3 phases:
1. Idle phase
2. DCbias phase
3. Txdata phase.
The Idle phase is used outside transmit packets. In this
phase the T_GFSK output state is defined by the
‘gfsk float’ bit in the Enable Register. If the ‘gfsk float’ bit is
set to a logic 0, the T_GFSK output is pulled to ground; if
set to a logic 1 the T_GFSK output is floating.
The DCbias phase is used during the transmit slot as
start-up phase before the transmit data. The DCbias
phase is active GFSK_DC_BIAS_Start delay following the
S_EN rising edge until the first transmit data bit on
TX_DATA.
During this phase a DC bias is generated by the GFSK
filter, which is achieved by selecting the GFSK table
mid-value as the output of the GFSK filter.
2001 Jun 19
PARAMETER
Bluetooth Adapter IC
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
10
11
12
13
14
17
18
1
2
3
4
5
6
7
8
9
T_GFSK
SYNTH_ON rising edge to 3-wire serial data
SYNTH_ON rising edge to REFCLK start
S_EN falling edge to REFCLK stop delay
S_EN falling edge to RSSI measurement
SYNTH_ON rising edge to S_EN rising edge
S_EN width
SYNTH_ON falling edge to S_EN pulse rising edge
SYNTH_ON falling edge to S_EN pulse rising edge
S_EN pulse width
SYNTH_ON rising edge to T_GFSK DC bias and TXCLK
enable
TX_DATA digital in to T_GFSK analog out delay
S_EN pulse falling edge to T_GFSK LOW and TXCLK
disable
S_EN falling edge to SLCCTR rising edge
PX_ON rising edge to SLCCTR falling edge
SYNTH_ON rising edge to T_SW rising edge
S_EN pulse falling edge to T_SW falling edge
DESCRIPTION
10
The Txdata phase is used when TXDATA is present.
In this phase the TX_DATA is fed into the GFSK filter. The
presence of TXDATA is determined by detecting the first
TXDATA edge. The end of the TXDATA is detected by the
end of packet from the baseband controller. To not lose
TXDATA information in the T_GFSK output, due to the
data detection, the data from the GFSK input is delayed
with 1-bit.
The T_GFSK output requires an external low-pass filter.
The reference voltage for the T_GFSK comes directly from
the V
relation to a variation in the T_GFSK levels. The V
power supply should be provided from a voltage reference.
The TX_CLK output is activated during the DC_BIAS
phase and the Txdata phase.
DDA
power supply. Any variation on V
0.35
S_EN start
2
RSSI_start
S_EN start
S_EN width
S_EN pulse start
S_EN pulse start
2
GFSK_DC_bias start
14
0
SLCCTR start
0
T_SW start
0
VALUE
Preliminary specification
PCF26100
13 MHz cycles
DDA
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
has a direct
UNIT
DDA