PCF8531U2D NXP [NXP Semiconductors], PCF8531U2D Datasheet - Page 28

• Manufacturer Part Number: PCF8531U2D
• Description: 34 x 128 pixel matrix driver Single-chip LCD controller and driver
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
10. I
PCF8531
Product data sheet
2
C-bus interface
10.1.1 Bit transfer
10.1.2 START and STOP conditions
10.1.3 System configuration
10.1 Characteristics of the I
The I
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only
when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P). The START and STOP conditions are shown in
The system configuration is shown in
Fig 14. Bit transfer
Fig 15. Definition of START and STOP conditions
•
•
•
•
Transmitter: the device that sends the data to the bus
Receiver: the device that receives the data from the bus
Master: the device that initiates a transfer, generates clock signals and terminates a
transfer
Slave: the device addressed by a master
2
C-bus is for bidirectional, two-line communication between different ICs or modules.
SDA
SCL
START condition
All information provided in this document is subject to legal disclaimers.
SDA
SCL
S
Rev. 6 — 16 May 2011
2
C-bus
data valid
data line
stable;
Figure
Figure
16.
allowed
change
of data
14).
34 x 128 pixel matrix driver
Figure
STOP condition
mbc621
P
15.
PCF8531
© NXP B.V. 2011. All rights reserved.
mbc622
SDA
SCL
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