M41T0 STMICROELECTRONICS [STMicroelectronics], M41T0 Datasheet - Page 12

• Manufacturer Part Number: M41T0
• Description: SERIAL REAL-TIME CLOCK
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M41T0
READ Mode
In this mode, the master reads the M41T0 slave
after setting the slave address (see
lowing the WRITE Mode Control Bit (R/W = 0) and
the Acknowledge Bit, the word address An is writ-
ten to the on-chip address pointer. Next the
START condition and slave address are repeated,
followed by the READ Mode Control Bit (R/W = 1).
At this point, the master transmitter becomes the
master receiver. The data byte which was ad-
dressed will be transmitted and the master receiv-
er will send an Acknowledge Bit to the slave
transmitter. The address pointer is only increment-
ed on reception of an Acknowledge Bit. The
M41T0 slave transmitter will now place the data
byte at address A
ceiver reads and acknowledges the new byte and
the address pointer is incremented to A
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter.
Figure 9. Slave Address Location
12/20
n+1
on the bus. The master re-
START
Figure
n+2
9.). Fol-
.
1
1
SLAVE ADDRESS
0
1
An alternate READ Mode may also be implement-
ed, whereby the master reads the M41T0 slave
without first writing to the (volatile) address point-
er. The first address that is read is the last one
stored in the pointer (see
WRITE Mode
In this mode the master transmitter transmits to
the M41T0 slave receiver. Bus protocol is shown
in
dition and slave address, a logic '0' (R/W = 0) is
placed on the bus and indicates to the addressed
device that word address An will follow and is to be
written to the on-chip address pointer. The data
word to be written to the memory is strobed in next
and the internal address pointer is incremented to
the next memory location within the RAM on the
reception of an acknowledge clock. The M41T0
slave receiver will send an acknowledge clock to
the master transmitter after it has received the
slave address and again after it has received the
word address and each data byte (see
0
Figure 12., page
0
0
R/W
A
AI00602
13. Following the START con-
Figure 11., page
Figure
13).
9.).