ADCS9888CVH-140 NSC [National Semiconductor], ADCS9888CVH-140 Datasheet - Page 27

• Manufacturer Part Number: ADCS9888CVH-140
• Description: 205/170/140 MSPS Video Analog Front End
• Manufacturer: NSC [National Semiconductor]

Application Information
4.1.6 Pre-Coast and Post-Coast
When Vsync is used as the coast source, the coast signal
can be extended earlier and later by setting the Pre-Coast
and Post-Coast settings in Registers 12h and 13h. This
feature requires the chip to calculate the number of Hsync
pulses (lines) per Vsync (frame). An 11 bit counter is pro-
vided to support frame sizes up to 2048 lines (active lines
plus vertical blanking overhead).
Once the frame size has been calculated, the chip will an-
ticipate when the next VSYNC begins, and the coast signal
can be generated up to 255 lines earlier than the anticipated
Vsync. Similarly, the Post-coast setting allows the PLL coast
UXGA
Note: * Alternate pixel sampling mode. See section 4.2.1
SVGA
SXGA
Mode
VGA
XGA
(Pixel/Lines)
1280 x 1024
1600 x 1200
Resolution
1024 x 768
640 x 480
800 x 600
Refresh
Rate
Hz
60
72
75
85
56
60
72
75
85
60
70
75
80
85
60
75
85
60
65
70
75
85
(Continued)
Clock Generation Setting
Frequency
HSYNC
106.3
31.5
37.7
37.5
43.3
35.1
37.9
48.1
46.9
53.7
48.4
56.5
60.0
64.0
68.3
64.0
80.0
91.1
75.0
81.3
87.5
93.8
kHz
27
signal to be maintained as many as 255 lines following the
de-assertion of Vsync.
4.1.7 Coast Polarity Detection
The coast signal input to the Clock Generator can be an
active high or active low signal. A polarity detection circuit
determines the polarity of the Coast signal. The polarity is
determined by observing the high/low duty cycle of the
COAST signal to determine whether the signal is mostly high
or mostly low. If the signal is mostly low, then the polarity is
set as Positive. If the signal is mostly high, then the polarity
is set to Negative. (0 = Negative, 1 = Positive) The results of
this detection are sent to Register 14h, Bit 0.
108.000
135.000
157.500
162.000
175.500
189.000
202.500
229.500
25.175
31.500
31.500
36.000
36.000
40.000
50.000
49.500
56.250
65.000
75.000
78.750
85.500
94.500
Pixel
Rate
MHz
*
RNGE
VCO
00
00
00
00
00
00
01
01
01
01
01
01
10
10
10
10
11
11
11
11
11
10
CPMP
VCO
010
100
100
101
100
100
100
100
101
101
011
011
011
011
011
011
011
011
011
011
011
011
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DIV Setting
1023
1055
1039
1055
1047
1343
1327
1311
1335
1375
1687
1687
1727
2159
2159
2159
2159
1079
PLL
799
831
839
831