PCA9306D PHILIPS [NXP Semiconductors], PCA9306D Datasheet

PCA9306D

Manufacturer Part Number

PCA9306D

Description

Dual bidirectional I2C-bus and SMBus voltage-level translator

Manufacturer

PHILIPS [NXP Semiconductors]

Datasheet

1.PCA9306D.pdf (21 pages)

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1. General description

The PCA9306 is a dual bidirectional I

enable (EN) input, and is operational from 1.1 V to 3.6 V (V

The PCA9306 allows bidirectional voltage translations between 1.2 V and 5 V without the

use of a direction pin. The low ON-state resistance (R

to be made with minimal propagation delay. When EN is HIGH, the translator switch is on,

and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2 I/O, respectively,

allowing bidirectional data ﬂow between ports. When EN is LOW, the translator switch is

off, and a high-impedance state exists between ports.

In I

and bus length. Using the PCA9306 enables the system designer to isolate two halves of

a bus, thus more I

the enable pin. The PCA9306 is not a bus buffer like the PCA9509 or PCA9517 that

provides level translation and physically isolates the capacitance to either side of the bus

even when both sides are connected.

The PCA9306 can also be used to run two buses, one at 400 kHz operating frequency

and the other at 100 kHz operating frequency. If the two buses are operating at different

frequencies, the 100 kHz bus must be isolated when the 400 kHz operation of the other

bus is required. If the master is running at 400 kHz, the maximum system operating

frequency may be less than 400 kHz because of the delays added by the translator.

As with the standard I

HIGH levels on the translator’s bus. The PCA9306 has a standard open-collector

conﬁguration of the I

but each side of the translator must have a pull-up resistor. The device is designed to work

with Standard-mode, Fast-mode and Fast mode Plus I

SMBus devices.

When the SDA1 or SDA2 port is LOW, the clamp is in the ON-state and a low resistance

connection exists between the SDA1 and SDA2 ports. Assuming the higher voltage is on

the SDA2 port when the SDA2 port is HIGH, the voltage on the SDA1 port is limited to the

voltage set by VREF1. When the SDA1 port is HIGH, the SDA2 port is pulled to the drain

pull-up supply voltage (V

translation between higher and lower voltages selected by the user without the need for

directional control. The SCL1/SCL2 channel also functions as the SDA1/SDA2 channel.

bias(ref)(2)

PCA9306

Dual bidirectional I

Rev. 02 — 21 February 2007

C-bus applications, the bus capacitance limit of 400 pF restricts the number of devices

C-bus devices or longer trace length can be accommodated by using

C-bus. The size of these pull-up resistors depends on the system,

C-bus system, pull-up resistors are required to provide the logic

pu(D)

) by the pull-up resistors. This functionality allows a seamless

C-bus and SMBus voltage-level translator

C-bus and SMBus voltage-level translator with an

C-bus devices in addition to

) of the switch allows connections

ref(1)

) and 2.3 V to 5.5 V

Product data sheet

Related parts for PCA9306D

PCA9306D Summary of contents

Page 1

PCA9306 Dual bidirectional I Rev. 02 — 21 February 2007 1. General description The PCA9306 is a dual bidirectional I enable (EN) input, and is operational from 1 3 bias(ref)(2) The PCA9306 allows bidirectional voltage ...

Page 2

NXP Semiconductors All channels have the same electrical characteristics and there is minimal deviation from one output to another in voltage or propagation delay. This is a beneﬁt over discrete transistor voltage translation solutions, since the fabrication of the switch ...

Page 3

... VSSOP8 [4] PCA9306GM P6X XQFN8 [1] Also known as MSOP8. [2] Same footprint and pinout as the Texas Instruments PCA9306DCT. [3] Same footprint and pinout as the Texas Instruments PCA9306DCU. [4] ‘X’ will change based on date code. 4. Functional diagram Fig 1. Logic diagram of PCA9306 (positive logic) PCA9306_2 Product data sheet ...

Page 4

... C-bus and SMBus voltage-level translator GND 1 VREF1 2 PCA9306DP SCL1 3 SDA1 4 002aac373 Fig 3. Pin conﬁguration for TSSOP8 (MSOP8) GND 1 VREF1 2 PCA9306DC1 3 SCL1 SDA1 4 002aab843 Fig 5. Pin conﬁguration for VSSOP8 (DC1) terminal 1 index area GND 1 PCA9306GM VREF1 2 SCL1 3 Transparent top view Fig 7. Pin conﬁ ...

Page 5

NXP Semiconductors 5.2 Pin description Table 2. Symbol GND VREF1 SCL1 SDA1 SDA2 SCL2 VREF2 EN 6. Functional description Refer to 6.1 Function table Table HIGH level LOW level. Input [1] EN ...

Page 6

NXP Semiconductors 7. Limiting values Table 4. In accordance with the Absolute Maximum Rating System (IEC 60134). Over operating free-air temperature range. Symbol V ref(1) V bias(ref)( I stg [1] The input ...

Page 7

NXP Semiconductors 9. Static characteristics Table 6. Static characteristics +85 C, unless otherwise speciﬁed. amb Symbol Parameter V input clamping voltage IK I HIGH-level input current IH C input capacitance on pin EN i(EN) C ...

Page 8

NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics (translating down +85 C, unless otherwise speciﬁed. Values guaranteed by design. amb Symbol Parameter Conditions ...

Page 9

NXP Semiconductors 11. Application information (1) The applied voltages at V Fig 9. Typical application circuit (switch always enabled) (1) In the Enabled mode, the applied enable voltage and the applied voltage at V Fig 10. Typical application circuit (switch ...

Page 10

NXP Semiconductors 11.1 Bidirectional translation For the bidirectional clamping conﬁguration (higher voltage to lower voltage or lower voltage to higher voltage), the EN input must be connected to VREF2 and both pins pulled to HIGH side V regulate the EN ...

Page 11

NXP Semiconductors Table 10. Calculated for V V pu( 3.3 V 2.5 V 1.8 V 1.5 V 1.2 V [1] + compensate for V PCA9306_2 Product data sheet Dual bidirectional I Pull-up resistor values = 0.35 ...

Page 12

NXP Semiconductors 12. Package outline SO8: plastic small outline package; 8 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT ...

Page 13

NXP Semiconductors TSSOP8: plastic thin shrink small outline package; 8 leads; body width pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 ...

Page 14

NXP Semiconductors TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0 pin 1 index 1 e DIMENSIONS (mm are the original dimensions ...

Page 15

NXP Semiconductors VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 ...

Page 16

NXP Semiconductors XQFN8: plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm terminal 1 index area metal area not for soldering 2 1 terminal 1 index area ...

Page 17

NXP Semiconductors 13. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow soldering description” . 13.1 Introduction to soldering Soldering ...

Page 18

NXP Semiconductors 13.4 Reﬂow soldering Key characteristics in reﬂow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including ...

Page 19

NXP Semiconductors Fig 16. Temperature proﬁles for large and small components For further information on temperature proﬁles, refer to Application Note AN10365 “Surface mount reﬂow soldering description” . 14. Abbreviations Table 13. Acronym CDM ESD HBM 2 I C-bus I/O ...

Page 20

NXP Semiconductors 16. Legal information 16.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualiﬁcation Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

Page 21

NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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