X9258_11 INTERSIL [Intersil Corporation], X9258_11 Datasheet - Page 14

• Manufacturer Part Number: X9258_11
• Manufacturer: INTERSIL [Intersil Corporation]

Test Circuit #3 SPICE Macro Model
AC Timing
NOTE:
16. A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.
SYMBOL
t
t
t
t
t
t
t
SU:WPA
HD:WPA
SU:STO
SU:STA
HD:STA
SU:DAT
HD:DAT
t
t
t
f
t
HIGH
LOW
CYC
t
SCL
t
BUF
DH
t
t
AA
T
R
F
I
R
H
Over recommended operating conditions, unless otherwise specified.
10pF
Clock Frequency
Clock Cycle Time
Clock High Time
Clock Low Time
Start Setup Time
Start Hold Time
Stop Setup Time
SDA Data Input Setup Time
SDA Data Input Hold Time
SCL and SDA Rise Time (Note 16)
SCL and SDA Fall Time (Note 16)
SCL Low to SDA Data Output Valid Time
SDA Data Output Hold Time
Noise Suppression Time Constant at SCL and SDA Inputs
Bus Free Time (Prior to any Transmission)
WP, A0, A1, A2 and A3 Setup Time
WP, A0, A1, A2 and A3 Hold Time
C
H
MACRO MODEL
R
TOTAL
14
R
W
25pF
C
W
C
10pF
L
R
L
PARAMETER
X9258
(Note 8)
2500
1300
1300
MIN
600
600
600
600
100
30
50
50
0
0
(Note 8)
MAX
400
300
300
900
April 14, 2011
UNIT
kHz
FN8168.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns