AD5066BRUZ-1 AD [Analog Devices], AD5066BRUZ-1 Datasheet - Page 6

• Manufacturer Part Number: AD5066BRUZ-1
• Description: Fully Accurate 16-Bit UnBuffered VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP
• Manufacturer: AD [Analog Devices]

AD5066
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
Figure 4. V
Table 4.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
1
2
3
4
5
6
7
8
8
9
10
11
12
13
14
15
Maximum SCLK frequency is 50 MHz at V
1
DD
= 2.7 V to 5.5 V. All specifications T
Limit at T
V
20
10
10
16.5
5
5
0
1.9
10.5
16.5
0
20
20
10
10
10.6
DD
= 2.7 V to 5.5 V
MIN
DD
, T
= 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.
MAX
Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications
TO OUTPUT
MIN
to T
PIN
MAX
50pF
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
us min
us min
ns min
ns min
ns min
ns min
ns min
ns min
us min
Rev. PrB | Page 6 of 20
C
, unless otherwise noted.
L
2mA
2mA
DD
) and timed from a voltage level of (V
I
I
OL
OH
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge set-up time
Data set-up time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time (single channel update)
Minimum SYNC high time ( all channel update)
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
LDAC pulse width low
SCLK falling edge to LDAC rising edge
CLR pulse width low
SCLK falling edge to LDAC falling edge
CLR pulse activation time
V
OH
(MIN)
Preliminary Technical Data
IL
+ V
IH
)/2. See Figure 3 and