ATF1502AS ATMEL [ATMEL Corporation], ATF1502AS Datasheet
ATF1502AS
Available stocks
Related parts for ATF1502AS
ATF1502AS Summary of contents
Page 1
... Pull-Up Option on JTAG Pins TMS and TDI • Advanced Power Management Features – Edge Controlled Power Down “L” – Individual Macrocell Power Option – Disable ITD on Global Clocks, Inputs and I/O High Performance 2 E PROM CPLD ATF1502AS Preliminary Rev. 0995A–04/98 1 ...
Page 2
... I/O 23 I/O I/O The ATF1502AS has bi-directional I/O pins and 4 dedicated input pins, depending on the type of device pack- age selected. Each dedicated pin can also serve as a glo- bal control signal; register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell ...
Page 3
... The XOR gate is also used to emulate T- and JK-type flip-flops. Flip Flop The ATF1502AS’s flip flop has very flexible data and con- trol functions. The data input can come from either the XOR gate, from a separate product term or directly from the I/O pin ...
Page 4
... OR of GCLEAR with a product term. The asynchronous preset (AP) can be a product term or always off. Output Select and Enable The ATF1502AS macrocell output can be selected as reg- istered or combinatorial. The buried feedback signal can be either combinatorial or registered signal regardless of whether the output is combinatorial or registered. ...
Page 5
... When using the ISP hardware or S/W to program the ATF1502AS devices, four I/0 pins must be reserved for the JTAG interface. However, the logic features the macrocells associated with these I/0 pins are still available to the design for burned logic functions ...
Page 6
... ISP) is not needed, then the four JTAG control pins are available as I/O pins. JTAG Boundary Scan Cell (BSC) Testing The ATF1502AS contains I/O pins and 4 input pins, depending on the and package type selected. Each input pin and I/O pin has its own boundary scan cell (BSC) in order to support boundary scan testing as described in detail by IEEE Standard 1149 ...
Page 7
DC Characteristics Symbol Parameter Input or I/O Low I IL Leakage Current Input or I/O High I IH Leakage Current Tri-State Output I OZ Off-State Current Power Supply Current, I CC1 Stand-by Power Supply Current, I CC2 Power Down Mode ...
Page 8
... Minimum Array Clock Period ACNT Maximum Internal Array f ACNT Clock Frequency ATF1502AS 8 *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any ...
Page 9
AC Characteristics (Continued) Symbol Parameter F Maximum Clock Frequency MAX t Input Pad and Buffer Delay IN t I/O Input Pad and Buffer Delay IO t Fast Input Delay FIN t Foldback Term Delay SEXP t Cascade Logic Delay PEXP ...
Page 10
... Switch Matrix Delay UIM (2) t Reduced-Power Adder RPA Notes: 1. See ordering information for valid part numbers. 2. The t parameter must be added to the t RPA power mode. Input Test Waveforms and Measurement Levels 1.5 ns typical R F ATF1502AS 10 -7 -10 -15 Min Max Min Max Min 4.0 5.0 4.5 5 ...
Page 11
... Power Down Mode The ATF1502AS includes an optional pin controlled power down feature.When this mode is enabled, the PD pin acts as the power down pin. When the PD pin is high, the device supply current is reduced to less than 3 mA. During power down, all output data and internal logic states are latched and held ...
Page 12
... BSC Configuration for Mac TDO D Q OEJ OUTJ TDI ATF1502AS 12 BSC for Dedicated Input Pin TDI 0 1 TDI CLOCK TDO Capture Update DR Clock Shift BSC for I/O Pins and Macrocells TDO Capture DR Clock Shift ...
Page 13
... PCI Compliance The ATF1502AS also supports the growing need in the industry to support the new Peripheral Component Inter- connect (PCI) interface standard in PCI-based designs and specifications. The PCI interface calls for high current driv- ers which are much larger than the traditional TTL drivers. ...
Page 14
... High) I Switching OL(AC) Current Low (Test Point) I Low Clamp Current CL SLEW Output Rise Slew Rate R SLEW Output Fall Slew Rate F Notes: 1. Equation 11 OUT 2. Equation 78 ATF1502AS 14 Conditions OUT mA OUT Conditions 0 < V 1.4 OUT -44+(V 1.4 < V < 2.4 OUT /0.024 3.1 < ...
Page 15
... ATF1502AS Dedicated Pinouts Dedicated Pin INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 I/O /GCLK3 I (1,2) I/O / TDI (JTAG) I/O / TMS (JTAG) I/O / TCK (JTAG) I/O / TDO (JTAG) GND V CCINT V CCIO N Signal Pins # User I/O Pins OE (1, 2) Global OE Pins GCLR Global Clear Pin GCLK ( Global Clock Pins PD (1, 2) Power down pins ...
Page 16
... ATF1502AS I/O Pinouts MC PLC A/PD1 8/TDI 32/TMS ATF1502AS 16 44-Pin PLCC ...
Page 17
... ATF1502AS-10 QI44 ATF1502AS-15 AC44 ATF1502AS-15 JC44 ATF1502AS-15 QC44 ATF1502AS-15 AI44 ATF1502AS-15 JI44 ATF1502AS-15 QI44 ATF1502ASL-20 AC44 ATF1502ASL-20 JC44 ATF1502ASL-20 QC44 ATF1502ASL-20 AI44 ATF1502ASL-20 JI44 ATF1502ASL-20 QI44 ATF1502ASL-25 AC44 ATF1502ASL-25 JC84 ATF1502ASL-25 QC44 ATF1502ASL-25 AI44 ATF1502ASL-25 JI84 ATF1502ASL-25 QI44 Package Type Package ...
Page 18
... Dimensions in Millimeters and (Inches)* * Controlling dimension: millimeters 44Q, 44 Lead, Plastic Gull Wing Quad Flat Package (PQFP) Dimensions in Inches and (Millimeters) * Controlling dimension: millimeters ATF1502AS 18 44J, 44-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-018 AC .045(1.14) X 30° - 45° ...