XCR3032-10PC44C XILINX [Xilinx, Inc], XCR3032-10PC44C Datasheet

XCR3032-10PC44C

Manufacturer Part Number

XCR3032-10PC44C

Description

32 Macrocell CPLD

Manufacturer

XILINX [Xilinx, Inc]

Datasheet

1.XCR3032-10PC44C.pdf (14 pages)

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DS038 (v1.3) October 9, 2000

Features

• Industry's first TotalCMOS™ PLD - both CMOS design

• Fast Zero Power (FZP™) design technique provides

• High speed pin-to-pin delays of 8ns

• Ultra-low static power of less than 35 A

• 100% routable with 100% utilization while all pins and

• Deterministic timing model that is extremely simple to

• Two clocks available

• Programmable clock polarity at every macrocell

• Support for asynchronous clocking

• Innovative XPLA™ architecture combines high speed

• 1000 erase/program cycles guaranteed

• 20 years data retention guaranteed

• Logic expandable to 37 product terms

• PCI compliant

• Advanced 0.5 E

• Security bit prevents unauthorized access

• Design entry and verification using industry standard

• Reprogrammable using industry standard device

• Innovative Control Term structure provides either sum

• Programmable global 3-state pin facilitates ‘bed of nails'

• Available in both PLCC and VQFP packages

Description

The XCR3032 CPLD (Complex Programmable Logic

Device) is the first in a family of CoolRunner

Xilinx. These devices combine high speed and zero power

in a 32 macrocell CPLD. With the FZP design technique,

the XCR3032 offers true pin-to-pin speeds of 8 ns, while

simultaneously delivering power that is less than 35 A at

standby without the need for “turbo bits” or other power

down schemes. By replacing conventional sense amplifier

methods for implementing product terms (a technique that

has been used in PLDs since the bipolar era) with a cas-

caded chain of pure CMOS gates, the dynamic power is

also substantially lower than any competing CPLD. These

devices are the first TotalCMOS PLDs, as they use both a

DS038 (v1.3) October 9, 2000

and process technologies

ultra-low power and very high speed

all macrocells are fixed

use

with extreme flexibility

and Xilinx CAE tools

programmers

terms or product terms in each logic block for:

- Programmable 3-state buffer

- Asynchronous macrocell register preset/reset

testing without using logic resources

This product has been discontinued. Please see

CMOS process

CPLDs from

www.xilinx.com

1-800-255-7778

www.xilinx.com/partinfo/notify/pdn0007.htm

14*

XCR3032: 32 Macrocell CPLD

Product Specification

CMOS process technology and the patented full CMOS

FZP design technique. For 5V applications, Xilinx also

offers the high speed XCR5032 CPLD that offers pin-to-pin

speeds of 6 ns.

The Xilinx FZP CPLDs utilize the patented XPLA

(eXtended Programmable Logic Array) architecture. The

XPLA architecture combines the best features of both PLA

and PAL type structures to deliver high speed and flexible

logic allocation that results in superior ability to make

design changes with fixed pinouts. The XPLA structure in

each logic block provides a fast 8 ns PAL path with five ded-

icated product terms per output. This PAL path is joined by

an additional PLA structure that deploys a pool of 32 prod-

uct terms to a fully programmable OR array that can allo-

cate the PLA product terms to any output in the logic block.

This combination allows logic to be allocated efficiently

throughout the logic block and supports as many as 37

product terms on an output. The speed with which logic is

allocated from the PLA array to an output is only 2.5 ns,

regardless of the number of PLA product terms used, which

results in worst case t

any other pin. In addition, logic that is common to multiple

outputs can be placed on a single PLA product term and

shared across multiple outputs via the OR array, effectively

increasing design density.

The XCR3032 CPLDs are supported by industry standard

CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor,

Synopsys, Synario, Viewlogic, and Synplicity), using text

(ABEL, VHDL, Verilog) and/or schematic entry. Design ver-

ification uses industry standard simulators for functional

and timing simulation. Development is supported on per-

sonal computer, Sparc, and HP platforms. Device fitting

uses a Xilinx developed tool, XPLA Professional (available

on the Xilinx web site).

The XCR3032 CPLD is reprogrammable using industry

standard device programmers from vendors such as Data

I/O, BP Microsystems, SMS, and others.

's of only 10.5 ns from any pin to

for details.

Related parts for XCR3032-10PC44C

XCR3032-10PC44C Summary of contents

Page 1

... Xilinx. These devices combine high speed and zero power macrocell CPLD. With the FZP design technique, the XCR3032 offers true pin-to-pin speeds of 8 ns, while simultaneously delivering power that is less than standby without the need for “turbo bits” or other power down schemes ...

Page 2

... PAL + 2.5 ns for the PLA LOGIC BLOCK ZIA 36 36 LOGIC BLOCK www.xilinx.com 1-800-255-7778 for details. of the XCR3032 device PD for the XCR3032 using six MC1 MC2 I/O MC16 MC1 MC2 I/O MC16 SP00439 2 ...

Page 3

... This product has been discontinued. Please see XCR3032: 32 Macrocell CPLD 36 ZIA INPUTS CONTROL 5 PAL ARRAY PLA ARRAY (32) Figure 2: Xilinx XPLA Logic block Architecture 3 www.xilinx.com/partinfo/notify/pdn0007.htm 6 www.xilinx.com 1-800-255-7778 for details. R SP00435A DS038 (v1.3) October 9, 2000 ...

Page 4

... There are two clocks (CLK0 and CLK1) available on the XCR3032 device. Clock 0 (CLK0) is designated as the "synchronous" clock and must be driven by an external source. Clock 1 (CLK1) can either be used as a synchro- nous clock (driven by an external source asyn- chronous clock (driven by a macrocell equation) ...

Page 5

... In the XPLA architecture, the user knows up front whether the design will meet system timing requirements. This is due to the simplicity of the timing model. For example, in the XCR3032 device, the user knows up front that if a given output uses five product terms or less, the t INPUT PIN ...

Page 6

... Table 1: I vs. Frequency (V = 3.3V, 25° Frequency (MHz Typical I (mA) 0.01 2.37 CC DS038 (v1.3) October 9, 2000 www.xilinx.com/partinfo/notify/pdn0007.htm FREQUENCY (MHz) = 3.3V, 25° 4.65 6.80 9.06 11.1 13.5 15.5 www.xilinx.com 1-800-255-7778 for details. XCR3032: 32 Macrocell CPLD TYPICAL 90 100 110 120 130 SP00443 80 90 100 110 120 17.4 20.0 22.1 24.4 26.6 130 28.5 6 ...

Page 7

... This product has been discontinued. Please see XCR3032: 32 Macrocell CPLD Absolute Maximum Ratings Symbol 2 V Supply voltage CC V Input voltage I V Output voltage OUT I Input current IN I Output current OUT T Maximum junction temperature J T Storage temperature str Notes: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. ...

Page 8

... One pin at a time for no longer than 1 second MHz AMB MHz AMB MHz AMB or ground. This parameter guaranteed by design and characterization, not testing. www.xilinx.com 1-800-255-7778 for details. XCR3032: 32 Macrocell CPLD Min. Max. Unit 0.8 2.0 -1.2 0 -10 10 ...

Page 9

... This product has been discontinued. Please see XCR3032: 32 Macrocell CPLD AC Electrical Characteristics Commercial 3.0V AMB Symbol t Propagation delay time, input (or feedback node) to output through PD_PAL PAL t Propagation delay time, input (or feedback node) to output through PD_PLA PAL + PLA t Clock to out (global synchronous clock from pin) ...

Page 10

Page 11

... This product has been discontinued. Please see XCR3032: 32 Macrocell CPLD AC Electrical Characteristics Industrial: - +85 C; 3.0V AMB Symbol t Propagation delay time, input (or feedback node) to output through PAL PD_PAL t Propagation delay time, input (or feedback node) to output through PD_PLA PAL + PLA t Clock to out (global synchronous clock from pin) ...

Page 12

... Figure 7: Voltage Waveform Table 2: t PD_PAL ( 25° SP00449A # of Outputs Typical (ns) www.xilinx.com 1-800-255-7778 for details. XCR3032: 32 Macrocell CPLD VALUES 390 390 Open Closed Closed Closed Closed Closed pF, and 3-state levels are SP00477 ...

Page 13

... XCR3032 Global, Power, and Ground Pins Pin Type IN0 IN1 VQ44 Notes IN2 42 IN3 43 gtsn 44 CLK0 1 CLK1 2 Vcc 3 GND (1) Global 3-State pin facilitates bed of nails testing without using logic resources ...

Page 14

... This product has been discontinued. Please see R Ordering Information Example: XCR3032 - Device Type Speed Options Speed Options -12 pin-to-pin delay -10 pin-to-pin delay - pin-to-pin delay Component Availability Pins Type Plastic VQFP Code VQ44 XCR3032 - ...

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