DSP56001FE33 MOTOROLA [Motorola, Inc], DSP56001FE33 Datasheet - Page 24

• Manufacturer Part Number: DSP56001FE33
• Description: 24-Bit General Purpose Digital Signal Processor
• Manufacturer: MOTOROLA [Motorola, Inc]

MOTOROLA
24
Num
55
56
57
59
60
61
62
63
64
65
66
Synchronous Clock Cycle — tSCC
Clock Low Period
Clock High Period
Output Data Setup to Clock Falling
Edge (Internal Clock)
Output Data Hold After Clock Rising
Edge (Internal Clock)
Input Data Setup Time Before Clock
Rising Edge (Internal Clock)
Input Data Not Valid Before Clock Ris-
ing Edge (Internal Clock)
Clock Falling Edge to Output Data
Valid (External Clock)
Output Data Hold After Clock Rising
Edge (External Clock)
Input Data Setup Time Before Clock
Rising Edge (External Clock)
Input Data Hold Time After Clock Ris-
ing Edge (External Clock)
(Vcc = 5.0 Vdc + 10%, T
cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles
tSCC = Synchronous Clock Cycle Time (for internal clock tSCC is determined by the SCI clock control register and Icyc.)
see SCI Figures 1 and 2)
Vcc = 5.0 Vdc + 5%, T
Characteristics
DSP56001 Electrical Characteristics
AC Electrical Characteristics - SCI Timing
J
J
= -40 to +105° C, CL = 50 pf + 1 TTL Load at 33 MHz,
= -40 to +105° C, CL = 50 pf + 1 TTL Load at 20.5 MHz and 27 MHz,
4
SCI Synchronous Mode Timing
4
+tcl+45
cyc+12
+tcl-50
*
*
-tcl-15
8
2
2
2
Min
cyc-20
cyc-20
*
*
*
*
30
40
—
—
cyc
cyc
cyc
cyc
20.5 MHz
+tcl-10
2
Max
*
63
—
—
—
—
—
—
—
—
—
cyc
4
4
+tcl+35
+tcl-39
*
*
-tcl-11
cyc+9
2
2
2
8
cyc-15
cyc-15
Min
*
*
*
*
—
—
23
31
cyc
cyc
cyc
cyc
27 MHz
+tcl-8
2
Max
*
48
—
—
—
—
—
—
—
—
—
cyc
4
4
+tcl+28
+tcl-31
*
*
cyc+8
2
2
2
8
-tcl-9
cyc-13
cyc-13
Min
*
*
*
19
25
*
—
—
cyc
cyc
cyc
cyc
33 MHz
2
+tcl-6
Max
*
39
—
—
—
—
—
—
—
—
—
cyc
DSP56001
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns