EP1K50 ALTERA [Altera Corporation], EP1K50 Datasheet - Page 28

• Manufacturer Part Number: EP1K50
• Description: 1. Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

1–28
IEEE Std. 1149.1 (JTAG) Boundary-Scan
Figure 1–6. JTAG Timing Waveforms
Table 1–13. JTAG Timing Parameters and Values
Configuration Handbook (Complete Two-Volume Set)
t
t
t
t
t
t
t
t
t
t
t
t
t
JCP
JCH
JCL
JPSU
JPH
JPCO
JPZX
JPXZ
JSSU
JSH
JSCO
JSZX
JSXZ
Symbol
Captured
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time
JTAG port hold time
JTAG port clock output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high-impedance to valid output
Update register valid output to high impedance
The enhanced configuration device provides JTAG BST circuitry that complies with
the IEEE Std. 1149.1-1990 specification. JTAG boundary-scan testing can be performed
before or after configuration, but not during configuration.
Figure 1–6
Driven
Table 1–13
device.
Signal
Signal
to be
to be
TMS
TDO
TCK
TDI
shows the timing requirements for the JTAG signals.
lists the timing parameters and values for the enhanced configuration
t
JCH
t
t
JSZX
JPZX
t
JCP
t
JSSU
Parameter
t
JCL
t
Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
JSH
t
t
JPCO
JSCO
t
JPSU
t
t
JPH
JSXZ
Min
100
50
50
20
45
—
—
—
20
45
—
—
—
t
JPXZ
IEEE Std. 1149.1 (JTAG) Boundary-Scan
© December 2009 Altera Corporation
Max
—
—
—
—
—
25
25
25
—
—
25
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns