DP83932B NSC [National Semiconductor], DP83932B Datasheet

DP83932B

Manufacturer Part Number

DP83932B

Description

SONICTM-16 Systems-Oriented Network Interface Controller

Manufacturer

NSC [National Semiconductor]

Datasheet

1.DP83932B.pdf (96 pages)

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C 1995 National Semiconductor Corporation

DP83916 SONIC

Systems-Oriented Network Interface Controller

General Description

The SONIC

Controller) is a second-generation Ethernet Controller de-

signed to meet the demands of today’s high-speed 16-bit

systems Its system interface operates with a high speed

DMA that typically consumes less than 8% of the bus band-

width Selectable bus modes provide both big and little endi-

an byte ordering and a clean interface to standard micro-

processors The linked-list buffer management system of

SONIC-16 offers maximum flexibility in a variety of environ-

ments from PC-oriented adapters to high-speed mother-

board designs Furthermore the SONIC-16 integrates a ful-

ly-compatible IEEE 802 3 Encoder Decoder (ENDEC) al-

lowing for a simple 2-chip solution for Ethernet when the

SONIC-16 is paired with the DP8392 Coaxial Transceiver

Interface

For increased performance the SONIC-16 implements a

unique buffer management scheme to efficiently process

receive and transmit packets in system memory No inter-

mediate packet copy is necessary The receive buffer man-

agement uses three areas in memory for (1) allocating addi-

tional resources (2) indicating status information and (3)

buffering packet data During reception the SONIC-16

stores packets in the buffer area then indicates receive

status and control information in the descriptor area The

system allocates more memory resources to the SONIC-16

by adding descriptors to the memory resource area The

transmit buffer management uses two areas in memory

System Diagram

TRI-STATE is a registered trademark of National Semiconductor Corporation

RIC

and SONIC

-16 are trademarks of National Semiconductor Corporation

-16 (Systems-Oriented Network Interface

TL F 11722

IEEE 802 3 Ethernet Thin-Ethernet 10BASE-T Station

-16

one for indicating status and control information and the

other for fetching packet data The system can create a

transmit queue allowing multiple packets to be transmitted

from a single transmit command The packet data can re-

side on any arbitrary byte boundary and can exist in several

non-contiguous locations

Features

23-bit non-multiplexed address 16-bit data bus

High-speed interruptible DMA

Linked-list buffer management maximizes flexibility

Two independent 32-byte transmit and receive FIFOs

Bus compatibility for all standard microprocessors

Supports big and little endian formats

Integrated IEEE 802 3 ENDEC

Complete address filtering for up to 16 physical and or

multicast addresses

32-bit general-purpose timer

Full-duplex loopback diagnostics

Fabricated in low-power CMOS

132 PQFP package

Full network management facilities support the IEEE

802 3 layer management standard

Integrated support for bridge and repeater applications

PRELIMINARY

RRD-B30M16 Printed in U S A

November 1995

TL F 11722– 1

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