DP83932C NSC [National Semiconductor], DP83932C Datasheet - Page 2

• Manufacturer Part Number: DP83932C
• Description: MHz SONICTM Systems-Oriented Network Interface Controller
• Manufacturer: NSC [National Semiconductor]

1 0 FUNCTIONAL DESCRIPTION
2 0 TRANSMIT RECEIVE IEEE 802 3
3 0 BUFFER MANAGEMENT
1 1 IEEE 802 3 ENDEC Unit
1 2 MAC Unit
1 3 Data Width and Byte Ordering
1 4 FIFO and Control Logic
1 5 Status and Configuration Registers
1 6 Bus Interface
1 7 Loopback and Diagnostics
1 8 Network Management Functions
2 1 Preamble and Start Of Frame Delimiter (SFD)
2 2 Destination Address
2 3 Source Address
2 4 Length Type Field
2 5 Data Field
2 6 FCS Field
2 7 MAC (Media Access Control) Conformance
3 1 Buffer Management Overview
3 2 Descriptor Areas
3 3 Descriptor Data Alignment
3 4 Receive Buffer Management
3 5 Transmit Buffer Management
FRAME FORMAT
1 1 1 ENDEC Operation
1 1 2 Selecting an External ENDEC
1 2 1 MAC Receive Section
1 2 2 MAC Transmit Section
1 4 1 Receive FIFO
1 4 2 Transmit FIFO
1 7 1 Loopback Procedure
3 2 1 Naming Convention for Descriptors
3 2 2 Abbreviations
3 2 3 Buffer Management Base Addresses
3 4 1 Receive Resource Area (RRA)
3 4 2 Receive Buffer Area (RBA)
3 4 3 Receive Descriptor Area (RDA)
3 4 4 Receive Buffer Management Initialization
3 4 5 Beginning of Reception
3 4 6 End of Packet Processing
3 4 7 Overflow Conditions
3 5 1 Transmit Descriptor Area (TDA)
3 5 2 Transmit Buffer Area (TBA)
3 5 3 Preparing to Transmit
3 5 4 Dynamically Adding TDA Descriptors
Table of Contents
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4 0 SONIC REGISTERS
5 0 BUS INTERFACE
6 0 NETWORK INTERFACING
7 0 AC AND DC SPECIFICATIONS
8 0 AC TIMING TEST CONDITIONS
4 1 The CAM Unit
4 2 Status Control Registers
4 3 Register Description
5 1 Pin Configurations
5 2 Pin Description
5 3 System Configuration
5 4 Bus Operations
6 1 Manchester Encoder and Differential Driver
4 1 1 The Load CAM Command
4 3 1 Command Register
4 3 2 Data Configuration Register
4 3 3 Receive Control Register
4 3 4 Transmit Control Register
4 3 5 Interrupt Mask Register
4 3 6 Interrupt Status Register
4 3 7 Data Configuration Register 2
4 3 8 Transmit Registers
4 3 9 Receive Registers
4 3 10 CAM Registers
4 3 11 Tally Counters
4 3 12 General Purpose Timer
4 3 13 Silicon Revision Register
5 4 1 Acquiring the Bus
5 4 2 Block Transfers
5 4 3 Bus Status
5 4 4 Bus Mode Compatibility
5 4 5 Master Mode Bus Cycles
5 4 6 Bus Exceptions (Bus Retry)
5 4 7 Slave Mode Bus Cycle
5 4 8 On-Chip Memory Arbiter
5 4 9 Chip Reset
6 1 1 Manchester Decoder
6 1 2 Collision Translator
6 1 3 Oscillator Inputs
6 1 4 Power Supply Considerations