GD82551QM INTEL [Intel Corporation], GD82551QM Datasheet - Page 85

• Manufacturer Part Number: GD82551QM
• Description: Fast Ethernet Multifunction PCI/CardBus Controller
• Manufacturer: INTEL [Intel Corporation]

11.0
11.1
11.1.1
Datasheet
Table 42. Register 0: Control
PHY Unit Registers
The 82551QM provides status and accepts management information via the Management Data
Interface (MDI) within the CSR space.
Acronyms mentioned in the registers are defined as follows:
MDI Registers 0 - 7
Register 0: Control Register
SC -
RO -
E -
LL -
LH -
15
14
13
12
Bit(s)
Reset
Loopback
Speed Selection
Auto-Negotiation
Enable
self cleared
read only
EEPROM setting affects content
latch low
latch high
Name
This bit sets the status and control register of the PHY to
their default states and is self-clearing. The PHY returns
a value of one until the reset process has completed and
accepts a read or write transaction.
1 = PHY Reset
the TXD[3:0] signals to the receive data path. The PHY
unit’s receive circuitry is isolated from the network.
Note that this may cause the descrambler to lose
synchronization and produce 560 nanoseconds of “dead
time.”
Note also that the loopback configuration bit takes priority
over the Loopback MDI bit.
1 = Loopback enabled
0 = Loopback disabled (Normal operation)
This bit controls speed when Auto-Negotiation is disabled
and is valid on read when Auto-Negotiation is disabled.
1 = 100 Mbps
0 = 10 Mbps
This bit enables Auto-Negotiation. Bits 13 and 8, Speed
Selection and Duplex Mode, respectively, are ignored
when Auto-Negotiation is enabled.
1 = Auto-Negotiation enabled
0 = Auto-Negotiation disabled
This bit enables loopback of transmit data nibbles from
Description
Networking Silicon — 82551QM
Default
0
0
1
1
RW
SC
RW
RW
RW
R/W
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