ISL6263 INTERSIL [Intersil Corporation], ISL6263 Datasheet - Page 8

• Manufacturer Part Number: ISL6263
• Description: 5-Bit VID Single-Phase Voltage Regulator for IMVP-6+ Santa Rosa GPU Core
• Manufacturer: INTERSIL [Intersil Corporation]

Electrical Specifications
NOTES:
Functional Pin Descriptions
RBIAS (Pin 1) - Sets the internal 10µ
Connect a 150kΩ ±1% resistor from RBIAS to VSS.
SOFT (Pin 2) - Sets the output voltage slew-rate. Connect
an X5R or X7R ceramic capacitor from SOFT to VSS. The
SOFT pin is the non-inverting input of the error amplifier.
OCSET (Pin 3) - Sets the overcurrent threshold. Connect a
resistor from OCSET to VO.
VW (Pin 4) - Sets the static PWM switching frequency in
continuous conduction mode. Connect a resistor from VW to
COMP.
COMP (Pin 5) - Connects to the output of the control loop
error amplifier.
FB (Pin 6) - Connects to the inverting input of the control
loop error amplifier.
VDIFF (Pin 7) - Connects to the output of the VDIFF
differential-summing amplifier.
VSEN (Pin 8) - This is the V
socket Kelvin connection. Connects internally to one of two
non-inverting inputs of the VDIFF differential-summing
amplifier.
VR_ON Input High
AF_EN Input Low
AF_EN Input High
VR_ON Leakage
AF_EN Leakage
VID<4:0> Input Low
VID<4:0> Input High
FDE Input Low
FDE Input High
VID<4:0> Leakage
FDE Leakage
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
7. Limits established by characterization and are not production tested.
8. Limits should be considered typical and are not production tested.
and are not production tested.
PARAMETER
CC_SNS
8
These specifications apply for T
T
-10°C to +100°C. (Continued)
A
= +25°C, VDD = 5V, PVCC = 5V. Boldface limits apply over the operating temperature range,
input of the processor
A
V
current reference.
SYMBOL
V
V
I
I
I
I
VR_ONH
VR_ONL
AF_ENH
VR_ONH
AF_ENL
V
AF_ENH
V
AF_ENL
V
V
I
I
I
I
FDEH
FDEL
VIDH
FDEH
VIDL
FDEL
VIDH
VIDL
V
V
V
V
V
V
V
V
AF_EN
AF_EN
VR_ON
VR_ON
VID
VID
FDE
FDE
= 0V
= 1.0V
= 0V
= 1.0V
ISL6263
= 0V
= 3.3V
= 0V
= 3.3V
A
= -10°C to +100°C, unless otherwise stated. All typical specifications
TEST CONDITIONS
RTN (Pin 9) - This is the V
socket Kelvin connection. Connects internally to one of two
inverting inputs of the VDIFF differential-summing amplifier.
DROOP (Pin 10) - Connects to the output of the droop
differential amplifier and to one of two non-inverting inputs of
the VDIFF differential-summing amplifier.
DFB (Pin 11) - This is the feedback of the droop amplifier.
Connects internally to the inverting input of the droop
differential amplifier.
VO (Pin 12) - Connects to one of two inverting inputs of the
VDIFF differential-summing amplifier.
VSUM (Pin 13) - Connects to the non-inverting input of the
droop differential amplifier.
VIN (Pin 14) - Connects to the R
input voltage feed-forward. For optimum input voltage
transient response, connect near the drain of the high-side
MOSFETs.
VSS (Pin 15) - Analog ground.
VDD (Pin 16) - Input power supply for the IC. Connect to
+5VDC and decouple with at least a 1µF MLCC capacitor
from the VDD pin to the VSS pin.
(Note 6)
MIN
-1.0
-1.0
-1.0
-1.0
2.3
2.3
0.7
0.7
SS_SNS
-
-
-
-
-
-
-
3
PWM modulator providing
TYP
0.45
0.45
0.45
input of the processor
0
0
0
0
0
-
-
-
-
-
-
-
(Note 6)
MAX
1.0
1.0
0.3
0.3
1.0
1.0
1
-
-
-
-
-
-
-
-
June 10, 2010
UNITS
FN9213.2
µA
µA
µA
µA
µA
µA
µA
µA
V
V
V
V
V
V
V