SAK-XC161CJ-16F20F INFINEON [Infineon Technologies AG], SAK-XC161CJ-16F20F Datasheet - Page 43

• Manufacturer Part Number: SAK-XC161CJ-16F20F
• Description: 16-Bi t Single-Chip Microcontroller Preliminary
• Manufacturer: INFINEON [Infineon Technologies AG]

Preliminary
3.12
The Serial Data Link Module (SDLM) provides serial communication on a J1850 type
multiplexed serial bus via an external J1850 bus transceiver. The module conforms to
the SAE Class B J1850 specification for variable pulse width modulation (VPW).
General SDLM Features:
• Compliant to the SAE Class B J1850 specification (VPW)
• Class 2 protocol fully supported
• Variable Pulse Width (VPW) operation at 10.4 kbit/s
• High Speed 4X operation at 41.6 kbit/s
• Programmable Normalization Bit
• Programmable Delay for transceiver interface
• Digital Noise Filter
• Power Down mode with automatic wake-up support upon bus activity
• Single Byte Header and Consolidated Header supported
• CRC generation and checking
• Receive and transmit Block Mode
Data Link Operation Features:
• 11-Byte Transmit Buffer
• Double buffered 11-Byte receive buffer (optional overwrite enable)
• Support for In Frame Response (IFR) types 1, 2 and 3
• Transmit and Receiver Message Buffers configurable for either FIFO or Byte mode
• Advanced Interrupt Handling with 8 separately enabled sources:
• Automatic IFR transmission (Types 1 and 2) for 3-Byte consolidated headers
• User configurable clock divider
• Bus status flags (IDLE, EOF, EOD, SOF, Tx and Rx in progress)
Note: When the SDLM is used with the interface lines assigned to Port 4, the segment
Data Sheet
Error, format or bus shorted
CRC error
Lost Arbitration
Break received
In-Frame-Response request
Header received
Complete message received
Transmit successful
address output on Port 4 must be limited. CS lines can be used to increase the
total amount of addressable external memory.
Serial Data Link Module (SDLM)
39
Functional Description
Derivatives
V1.0, 2002-03
XC161