ADCMP606 AD [Analog Devices], ADCMP606 Datasheet

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ADCMP606

Manufacturer Part Number
ADCMP606
Description
Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators
Manufacturer
AD [Analog Devices]
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADCMP606BKSZ-REEL7
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Preliminary Technical Data
FEATURES
10 mV sensitivity rail to rail at V
Input common-mode voltage from −0.2 V to V
CML-compatible output stage
1 ns propagation delay
50 mW at 2.5 V
Shutdown pin (ADCMP607 only)
Single-pin control for programmable hysteresis and latch
Power supply rejection > 60 dB
−40°C to +125°C operation
APPLICATIONS
High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
Pulse spectroscopy
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators
Automatic test equipment (ATE)
GENERAL DESCRIPTION
The ADCMP606/ADCMP607 are very fast comparators
fabricated on Analog Devices’ proprietary XFCB2 process.
These comparators are exceptionally versatile and easy to use.
Features include an input range from V
low noise CML-compatible output drivers, and TTL-/CMOS-
compatible latch inputs with adjustable hysteresis and/or
shutdown inputs.
The device offers 1 ns propagation delay with 2 ps RMS random
jitter (RJ). Overdrive and slew rate dispersion are typically less
than 50 ps.
A flexible power supply scheme allows the devices to operate
with a single +2.5 V positive supply and a −0.5 V to +3.0 V
input signal range up to a +5.5 V positive supply with a −0.5 V
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
(ADCMP607 only)
CC
= 2.5 V
EE
− 0.5 V to V
CC
+ 0.2 V
CC
+ 0.5 V,
Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,
Single-Supply CML Comparators
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
to +6 V input signal range. The ADCMP607 features split
input/output supplies with no sequencing restrictions to support
a wide input signal range with independent output level control
and power savings.
The CML-compatible output stage is fully back-matched for
superior performance. The comparator input stage offers robust
protection against large input overdrive, and the outputs do not
phase reverse when the valid input signal range is exceeded. On
the ADCMP607, high speed latch and programmable hysteresis
features are also provided with a unique single-pin control option.
The ADCMP606 is available in a 6-lead SC70 package, and the
ADCMP607 is available in a 12-lead LSCFP package.
V
V
P
N
NONINVERTING
INVERTING
INPUT
INPUT
FUNCTIONAL BLOCK DIAGRAM
ADCMP606/ADCMP607
V
V
CCO
V
CCI
EE
Figure 2.LFCSP Pin Configuration
ADCMP606/
ADCMP607
1
2
3
©2006 Analog Devices, Inc. All rights reserved.
ADCMP607
(Not to Scale)
TOP VIEW
V
PIN 1
INDICATOR
Figure 1.
CCI
LE/HYS INPUT (ADCMP607 Only)
S
(ADCMP607 Only)
DN
INPUT (ADCMP607 Only)
9 V
8 LE/HYS
7 S
V
CML
CCO
EE
DN
www.analog.com
Q OUTPUT
Q OUTPUT

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ADCMP606 Summary of contents

Page 1

... On the ADCMP607, high speed latch and programmable hysteresis features are also provided with a unique single-pin control option. The ADCMP606 is available in a 6-lead SC70 package, and the ADCMP607 is available in a 12-lead LSCFP package. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. ...

Page 2

... ADCMP606/ADCMP607 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Electrical Characteristics ................................................................. 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 REVISION HISTORY 3/06—Revision PrA: Preliminary Version Preliminary Technical Data Application Information...................................................................9 Power/Ground Layout and Bypassing........................................9 CML-Compatible Output Stage ...

Page 3

... Differential Voltage Offset Voltage Bias Current Offset Current Capacitance Resistance, Differential Mode Resistance, Common Mode Active Gain Common-Mode Rejection Hysteresis LATCH ENABLE PIN CHARACTERISTICS (ADCMP606 Only HYSTERESIS MODE AND TIMING Hysteresis Mode Bias Voltage Minimum Resistor Value ...

Page 4

... ADCMP606/ADCMP607 Parameter AC PERFORMANCE Propagation Delay Propagation Delay Skew—Rising to Falling Transition Overdrive Dispersion Slew Rate Dispersion Pulse-Width Dispersion 10% to 90% Duty Cycle Dispersion Common-Mode Dispersion Toggle Rate Deterministic Jitter CML Outputs RMS Random Jitter Minimum Pulse Width Rise Time Fall Time Output skew ...

Page 5

... V) A CCI soldered in a circuit board for surface-mount packages. ±50 mA Table 3. Thermal Resistance −0 0.5 V Package Type CCO ±50 mA ADCMP606 SC70 6-lead ADCMP607 LSCFP 12-lead −0 0.5 V CCO 1 Measurement in still air. ±50 mA ±50 mA −40°C to +125°C 150°C − ...

Page 6

... TOP VIEW 5 EE (Not to Scale Figure 3. ADCMP606 Pin Configuration Table 4. ADCMP606 (SC70-6) Pin Function Descriptions Pin No. Mnemonic Description 1 Q Noninverting Output logic high if the analog voltage at the noninverting input, V than the analog voltage at the inverting input Negative Supply Voltage. ...

Page 7

... TYPICAL PERFORMANCE CHARACTERISTICS 3 25°C, unless otherwise noted. CCI CCO A Figure 5. Propagation Delay vs. Input Overdrive Figure 6. Propagation Delay vs. Input Common Mode Figure 7. Propagation Delay vs. Temperature Figure 8. Rise/Fall Time vs. Temperature Figure 10. Input Bias Current vs. Input Common Mode Rev. PrA | Page ADCMP606/ADCMP607 Figure 9. ...

Page 8

... ADCMP606/ADCMP607 Figure 11. Input Bias Current vs. Temperature Figure 12. Hysteresis vs Rev. PrA | Page Preliminary Technical Data Figure 13. Input Offset Voltage vs. Temperature ...

Page 9

... CML-COMPATIBLE OUTPUT STAGE Specified propagation delay dispersion performance can be achieved by using proper transmission line terminations. The outputs of the ADCMP606 and ADCMP607 are designed to drive 400 mV directly into a 50 Ω cable or into transmission lines terminated using either microstrip or strip line techniques with 50 Ω ...

Page 10

... Dispersion is defined as the variation in propagation delay as the input overdrive conditions are changed ( and Figure 16). ADCMP606/ADCMP607 dispersion is typically <TBD ps as the overdrive varies from 500 mV and the input slew rate varies from 2 V/ V/ns. This specification applies to both positive and negative signals because each device has very closely matched delays for positive-going and negative-going inputs, as well as very low output skews ...

Page 11

... At this point, normally V /2, the direction of the bias current reverses CC and the measured offset voltages and currents change. The ADCMP606/ADCMP607 slightly elaborate on this scheme. With V less than 4 V, this crossover is at the expected V CC but with V ...

Page 12

... CML OUTPUT 50Ω 50Ω CML OUTPUT CCO 50Ω 3.3V PECL Rev. PrA | Page Preliminary Technical Data 5V 50Ω ADCMP606 INPUT 2.5V ±50mV INPUT 2.5V 10kΩ REF 10kΩ ADCMP601 LE/HYS 10kΩ 150pF 100kΩ Figure 23. Oscillator and Pulse-Width Modulator 2. ...

Page 13

... Preliminary Technical Data TIMING INFORMATION Figure 26 illustrates the ADCMP606/ADCMP607 timing relationships. Table 6 provides definitions of the terms shown in the figure. LATCH ENABLE DIFFERENTIAL INPUT VOLTAGE Q OUTPUT Q OUTPUT Table 6. Timing Descriptions Symbol Timing t Input to output high delay PDH t Input to output low delay PDL ...

Page 14

... ADCMP606/ADCMP607 NOTES Preliminary Technical Data Rev. PrA | Page ...

Page 15

... Preliminary Technical Data NOTES Rev. PrA | Page ADCMP606/ADCMP607 ...

Page 16

... ADCMP606/ADCMP607 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05917-0-3/06(PrA) Preliminary Technical Data T Rev. PrA | Page ...

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