SSTL16857DGG PHILIPS [NXP Semiconductors], SSTL16857DGG Datasheet - Page 3

• Manufacturer Part Number: SSTL16857DGG
• Description: 14-bit SSTL_2 registered driver with differential clock inputs
• Manufacturer: PHILIPS [NXP Semiconductors]

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
4. The continuous current at V
Philips Semiconductors
PIN DESCRIPTION
FUNCTION TABLE
H = High voltage level
L = High voltage level
X = Don’t care
ABSOLUTE MAXIMUM RATINGS
NOTES:
1999 Sep 30
1, 2, 5, 6, 7, 10,
3, 8, 13, 17, 22,
4, 9, 12, 16, 21
PIN NUMBER
48, 47, 44, 43,
42, 41, 40, 33,
32, 31, 30, 29,
11, 14, 15, 18,
= High-to-Low transition
= Low-to-High transition
SYMBOL
SYMBOL
19, 20, 23, 24
14-bit SSTL_2 registered driver with
differential clock inputs
RESET
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C.
27, 36, 46
28, 37, 45
V
T
I
I
V
I
O
OUT
I
OK
OUT
STG
V
26, 25
H
H
H
L
CC
IK
I
34
35
38
39
L or H
CLK
Storage temperature range
Q1 – Q14
SYMBOL
D1 – D14
X
DC output diode current
RESET
DC input diode current
VREF
CLK+
V
CLK–
GND
Continuous current
V
DC output voltage
DC supply voltage
DDQ
INPUTS
DC input voltage
DC output current
CC
PARAMETER
PARAMETER
L or H
CC
LVCMOS asynchronous master
reset
(Active LOW)
SSTL_2 data inputs
SSTL_2 data outputs
SSTL_2 input reference level
Ground (0 V)
Positive supply voltage
Output supply voltage
Differential clock inputs
CLK
X
, V
DDQ
NAME AND FUNCTION
3
3
, or GND should not exceed 100 mA.
4
1, 2
D
X
H
X
L
OUTPUT
Q
Q
H
L
L
0
V
CC
3
V
CONDITION
CONDITION
O
, V
LOGIC DIAGRAM
= 0 to V
V
V
Note 3
DDQ
O
I
< 0
< 0
, or GND
DDQ
RESET
VREF
CLK+
CLK–
D10
D12
D13
D14
D11
AD
D1
D2
D4
D5
D6
D7
D8
D9
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
–0.5
–0.5
–0.5
MIN
–65
LIMITS
SSTL16857
V
V
DDQ
DDQ
Product specification
MAX
+150
+4.6
–50
–50
100
50
+ 0.5
+ 0.5
SW00312
Q10
Q11
Q12
Q13
Q14
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
UNIT
UNIT
mA
mA
mA
mA
V
V
V
C