AT24C02-10PA-2.7C ATMEL [ATMEL Corporation], AT24C02-10PA-2.7C Datasheet - Page 6

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AT24C02-10PA-2.7C

Manufacturer Part Number
AT24C02-10PA-2.7C
Description
Two-wire Automotive Serial EEPROM
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
Bus Timing
Figure 2. SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing
Figure 3. SCL: Serial Clock, SDA: Serial Data I/O
Note:
6
SDA
SCL
1. The write cycle time t
AT24C01A/02/04/08/16
WORDn
8th BIT
WR
is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
STANDBY MODE: The AT24C01A/02/04/08/16 features a low-power standby mode
which is enabled: (a) upon power-up and (b) after the receipt of the Stop bit and the
completion of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-
wire part can be reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.
ACK
CONDITION
STOP
t wr
(1)
CONDITION
START
3256F–SEEPR–10/04

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