M24128-BRBN6 STMICROELECTRONICS [STMicroelectronics], M24128-BRBN6 Datasheet

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M24128-BRBN6

Manufacturer Part Number
M24128-BRBN6
Description
256Kbit and 128Kbit Serial I2C Bus EEPROM With Three Chip Enable Lines
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
FEATURES SUMMARY
Table 1. Product List
June 2005
Compatible with I
Two-Wire I
Supports 400kHz Protocol
Single Supply Voltage:
Hardware Write Control
BYTE and PAGE WRITE (up to 64 Bytes)
RANDOM and SEQUENTIAL READ Modes
Self-Timed Programming Cycle
Automatic Address Incrementing
Enhanced ESD/Latch-Up Protection
More than 1 Million Erase/Write Cycles
More than 40-Year Data Retention
Reference
128 Kbits
256 Kbits
2.5 to 5.5V for M24128-BW, M24256-BW
1.8 to 5.5V for M24128-BR, M24256-BR
2
C Serial Interface
2
C Extended Addressing
M24128-BW
M24128-BR
M24256-BW
M24256-BR
256Kbit and 128Kbit Serial I²C Bus EEPROM
Part Number
M24128-BW, M24128-BR
M24256-BW, M24256-BR
Figure 1. Packages
With Three Chip Enable Lines
TSSOP8 (DW)
8
150 mil width
200 mil width
169 mil width
8
PDIP8 (BN)
SO8 (MW)
SO8 (MN)
8
1
1
1
1/25

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M24128-BRBN6 Summary of contents

Page 1

... Compatible with I C Extended Addressing 2 Two-Wire I C Serial Interface Supports 400kHz Protocol Single Supply Voltage: – 2.5 to 5.5V for M24128-BW, M24256-BW – 1.8 to 5.5V for M24128-BR, M24256-BR Hardware Write Control BYTE and PAGE WRITE ( Bytes) RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle Automatic Address Incrementing ...

Page 2

... M24128-BW, M24128-BR, M24256-BW, M24256-BR TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. DIP, SO and TSSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Serial Clock (SCL Serial Data (SDA Chip Enable (E0, E1, E2 Write Control (WC Figure 4. Maximum RP Value versus Bus Parasitic Capacitance (C) for an I2C Bus . . . . . . . . . . . 5 Figure 5 ...

Page 3

... Table 11. Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 12. DC Characteristics (M24128-BW, M24256-BW Table 13. DC Characteristics (M24128-BR, M24256-BR Table 14. AC Characteristics ( M24128-BW, M24256-BW Table 15. AC Characteristics (M24128-BR, M24256-BR Figure 11.AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 12.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 19 Table 16. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 19 Figure 13.SO8 narrow – ...

Page 4

... M24128-BW, M24128-BR, M24256-BW, M24256-BR SUMMARY DESCRIPTION 2 These I C-compatible electrically erasable pro- grammable memory (EEPROM) devices are orga- nized as 32K x 8 bits (M24256-BW and M24256- BR) and 16K x 8 bits (M24128-BW and M24128- BR). Figure 2. Logic Diagram E0-E2 M24256-B SCL M24128 Table 2. Signal Names ...

Page 5

... M24128-BW, M24128-BR, M24256-BW, M24256-BR Chip Enable (E0, E1, E2). These input signals are used to set the value that looked for on the three least significant bits (b3, b2, b1) of the 7- bit Device Select Code. These inputs must be tied Code. When not connected (left floating), these in- indicates how the puts are read as Low (0,0,0) ...

Page 6

... M24128-BW, M24128-BR, M24256-BW, M24256-BR 2 Figure Bus Protocol SCL SDA START Condition SCL MSB SDA START Condition 1 SCL MSB SDA Table 3. Device Select Code b7 Device Select Code 1 Note: 1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared against the respective external pins on the memory device. ...

Page 7

... Note M24128-BW, M24128-BR, M24256-BW, M24256-BR Data (SDA) Low to acknowledge the receipt of the eight data bits. Data Input During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) ...

Page 8

... M24128-BW, M24128-BR, M24256-BW, M24256-BR Figure 6. Write Mode Sequences with WC=1 (data write inhibited) WC BYTE WRITE DEV SEL WC PAGE WRITE DEV SEL WC (cont'd) NO ACK PAGE WRITE (cont'd) Write Operations Following a Start condition the bus master sends a Device Select Code with the R/W bit (RW) reset to 0 ...

Page 9

... BYTE WRITE WC PAGE WRITE WC (cont'd) PAGE WRITE (cont'd) M24128-BW, M24128-BR, M24256-BW, M24256-BR data starts to become overwritten in an implemen- tation dependent way. The bus master sends from bytes of data, each of which is acknowledged by the device if Write Control (WC) is Low. If Write Control (WC) is ...

Page 10

... M24128-BW, M24128-BR, M24256-BW, M24256-BR Figure 8. Write Cycle Polling Flowchart using ACK First byte of instruction with already decoded by the device NO ReSTART STOP Minimizing System Delays by Polling On ACK During the internal Write cycle, the device discon- nects itself from the bus, and writes a copy of the data from its internal latches to the memory cells ...

Page 11

... Stop condition. Then, the bus master sends another Start condition, and repeats the Device Select Code, with the RW bit set to 1. The device acknowledges this, and out- M24128-BW, M24128-BR, M24256-BW, M24256-BR ACK NO ACK DATA OUT R/W ACK ...

Page 12

... M24128-BW, M24128-BR, M24256-BW, M24256-BR Sequential Read This operation can be used after a Current Ad- dress Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the de- vice continues to output the next byte in sequence. ...

Page 13

... Note: 1. Compliant with JEDEC Std J-STD-020C (for small body, Sn- assembly), the ST ECOPACK the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU 2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500 , R2=500 ) M24128-BW, M24128-BR, M24256-BW, M24256-BR this specification, is not implied. Exposure to Ab- solute Maximum Rating conditions for extended periods may affect device reliability ...

Page 14

... AC Characteristic tables that follow are de- rived from tests performed under the Measure- Table 8. Operating Conditions (M24128-BW, M24256-BW) Symbol V Supply Voltage CC T Ambient Operating Temperature A Table 9. Operating Conditions (M24128-BR, M24256-BR) Symbol V Supply Voltage CC T Ambient Operating Temperature A Table 10. AC Measurement Conditions Symbol ...

Page 15

... Input Impedance (WC Pulse width ignored t NS (Input Filter on SCL and SDA) Note 25° 400kHz A 2. Sampled only, not 100% tested. Table 12. DC Characteristics (M24128-BW, M24256-BW) Symbol Parameter Input Leakage Current I LI (SCL, SDA) I Output Leakage Current LO I Supply Current ...

Page 16

... M24128-BW, M24128-BR, M24256-BW, M24256-BR Table 14. AC Characteristics ( M24128-BW, M24256-BW) Symbol Alt Clock Frequency C SCL t t Clock Pulse Width High CHCL HIGH t t Clock Pulse Width Low CLCH LOW t t Clock Rise Time CH1CH2 Clock Fall Time CL1CL2 SDA Rise Time ...

Page 17

... Table 15. AC Characteristics (M24128-BR, M24256-BR) Symbol Alt Clock Frequency C SCL t t Clock Pulse Width High CHCL HIGH t t Clock Pulse Width Low CLCH LOW t t Clock Rise Time CH1CH2 Clock Fall Time CL1CL2 SDA Rise Time t R DH1DH2 ...

Page 18

... M24128-BW, M24128-BR, M24256-BW, M24256-BR Figure 11. AC Waveforms tCHCL SCL tDLCL SDA In tCHDX START Condition SCL SDA In tCHDH STOP Condition SCL tCLQV SDA Out 18/25 tCLCH tCLDX tDXCX SDA Change SDA Input tW Write Cycle tCLQX Data Valid tCHDH tDHDL STOP START Condition Condition ...

Page 19

... Figure 12. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline Note: Drawing is not to scale. Table 16. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data Symb. Typ 3.30 b 0.46 b2 1.52 c 0.25 D 9.27 E 7.87 E1 6.35 e 2. 3.30 M24128-BW, M24128-BR, M24256-BW, M24256- Min. Max. 5.33 0.38 2.92 4.95 0.36 0.56 1.14 1.78 0.20 0.36 9.02 10.16 7.62 8 ...

Page 20

... M24128-BW, M24128-BR, M24256-BW, M24256-BR Figure 13. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline SO-a Note: Drawing is not to scale. Table 17. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data Symb. Typ. ...

Page 21

... SO-b Note: Drawing is not to scale. Table 18. SO8 wide – 8 lead Plastic Small Outline, 200 mils body width, Package Mechanical Data Symb. Typ 0. 1. M24128-BW, M24128-BR, M24256-BW, M24256- Min. Max. 2.03 0.10 0.25 1.78 0.35 0.45 – – 5.15 5.35 5.20 5.40 – ...

Page 22

... M24128-BW, M24128-BR, M24256-BW, M24256-BR Figure 15. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline A CP Note: Drawing is not to scale. Table 19. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data Symbol Typ 1.000 3.000 e 0.650 E 6.400 E1 4.400 L 0.600 L1 1 ...

Page 23

... T = Tape and Reel Packing Plating Technology blank = Standard SnPb plating Lead-Free and RoHS compliant For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office. M24128-BW, M24128-BR, M24256-BW, M24256-BR M24256 – ...

Page 24

... Document reformatted. Parameters changed are: 1 million Erase/Write cycle endurance and 5 18-Oct-2002 3.0 ms write time for M24128-B and M24128-BW products with process letter "B". Superfluous (and incorrectly present) 100kHz AC Characteristics table for M24256-BR 20-Nov-2002 3.1 removed. Initial delivery state specified. -R and -S ranges are no longer Preliminary Data. Package 02-Jun-2003 3 ...

Page 25

... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America M24128-BW, M24128-BR, M24256-BW, M24256-BR All other names are the property of their respective owners © ...

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