M95256-R STMICROELECTRONICS [STMicroelectronics], M95256-R Datasheet
M95256-R
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M95256-R Summary of contents
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... Compatible with SPI bus serial interface (positive clock SPI modes) ■ Single supply voltage: – 4.5 to 5.5 V for M95256 – 2.5 to 5.5 V for M95256-W – 1.8 to 5.5 V for M95256-R ■ High speed – 5 MHz clock rate write time ■ Status Register ■ ...
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... CC Operating supply voltage Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 M95256, M95256-W, M95256-R ...
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... M95256, M95256-W, M95256-R 5.6 Write to Memory Array (WRITE 5.6.1 6 Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 ECC (error correction code) and Write cycling . . . . . . . . . . . . . . . . . . . 23 Contents ...
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... Table 5. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 7. Operating conditions (M95256 Table 8. Operating conditions (M95256- Table 9. Operating conditions (M95256-R Table 10. AC measurement conditions Table 11. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 12. DC characteristics (M95256, device grade 3 Table 13. DC characteristics (M95256-W, device grade Table 14. ...
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... M95256, M95256-W, M95256-R List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. SO and TSSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 6. Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 8. Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 9 ...
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... Description 1 Description The M95256, M95256-W and M95256-R are electrically erasable programmable memory (EEPROM) devices. They are accessed by a high speed SPI-compatible bus. Their memory array is organized as 32768 x 8 bits. The device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in The device is selected when Chip Select (S) is taken low ...
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... M95256, M95256-W, M95256-R Table 1. Signal names Signal name HOLD Function Serial Clock Serial Data input Serial Data output Chip Select Write Protect Hold Supply voltage Ground Description Direction Input Input Output Input Input Input 7/43 ...
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... Memory organization 2 Memory organization The memory is organized as shown in Figure 3. Block diagram HOLD W Control Logic Address Register 8/43 Figure 3. I/O Shift Register and Counter M95256, M95256-W, M95256-R High Voltage Generator Data Register Status Register 1 Page X Decoder Size of the Read only EEPROM area AI01272C ...
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... M95256, M95256-W, M95256-R 3 Signal description See Figure 1: Logic diagram connected to this device. 3.1 Serial Data output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). 3.2 Serial Data input (D) This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written ...
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... CC CC (min), V (max)] range must be applied (see CC CC continuously rises from V CC (min has reached the power on reset threshold voltage (this threshold is CC operating voltage defined in CC M95256, M95256-W, M95256-R CC Table 7, Table During this SS CC voltage ...
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... M95256, M95256-W, M95256-R ● deselected (at next power-up, a falling edge is required on Chip Select (S) before any instruction can be started). ● not in the Hold condition ● Status register: – the Write Enable Latch (WEL) is reset to 0 – the Write In Progress (WIP) is reset to 0 – ...
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... Operating features Figure 4. Hold condition activation C HOLD 12/43 M95256, M95256-W, M95256-R Hold Condition Hold Condition AI02029D ...
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... SPI bus. Table 2. Write-protected block size Status Register bits BP1 (RDSR). Protected block BP0 0 none 1 Upper quarter 0 Upper half 1 Whole memory Operating features Protected array addresse M95256, M95256-W, M95256-R none 6000h - 7FFFh 4000h - 7FFFh 0000h - 7FFFh 13/43 ...
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... Write to Memory Array 5, to send this instruction to the device, Chip Select (S) is driven low Instruction D High Impedance Q M95256, M95256-W, M95256-R Table 3. Table 3), the device automatically Instruction format 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010 5 ...
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... M95256, M95256-W, M95256-R 5.2 Write Disable (WRDI) One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in Figure and the bits of the instruction byte are shifted in, on Serial Data input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven high ...
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... Write Status Register (WRSR) instruction is no longer accepted for execution. Table 4. Status Register format b7 SRWD Status Register Write Protect 16/43 Table 4) becomes protected against Write M95256, M95256-W, M95256-R Figure 7. BP1 BP0 WEL Block Protect Bits Write Enable Latch Bit Write In Progress Bit b0 WIP ...
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... M95256, M95256-W, M95256-R Figure 7. Read Status Register (RDSR) sequence High Impedance Instruction Status Register Out MSB Instructions Status Register Out MSB 7 AI02031E 17/43 ...
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... Status Register (WRSR) instruction, including the t The instruction sequence is shown in 18/43 and Table 19), at the end of which the Write in Progress (WIP) bit is reset Table 4. Figure 8. M95256, M95256-W, M95256-R (as specified and is 0 when it is completed. When the W Table 5). In this mode, the Write Write cycle. W Table ...
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... M95256, M95256-W, M95256-R Table 5. Protection modes SRWD W signal bit defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in The protection features of the device are summarized in When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial ...
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... Instructions Figure 8. Write Status Register (WRSR) sequence 20/ Instruction Register High Impedance MSB M95256, M95256-W, M95256-R Status AI02282D ...
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... M95256, M95256-W, M95256-R 5.5 Read from Memory Array (READ) As shown in Figure The bits of the instruction byte and address bytes are then shifted in, on Serial Data input (D). The address is loaded into an internal address register, and the byte of data at that address is shifted out, on Serial Data output (Q). ...
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... Chip Select (S) is driven high after the eighth bit of the data byte Instruction 16-Bit Address High Impedance M95256, M95256-W, M95256-R (as specified in Table 16, Table WC Figure 11, the next byte Data Byte ...
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... ECC bits), that is, the addressed byte is cycled together with the three other bytes making up the word therefore recommended to write by word (4 bytes) in order to benefit from the larger amount of Write cycles. The M95256-W6 and M95256-R6 devices are qualified at 1 million (1 000 000) Write cycles, using a cycling routine that writes to the device by multiples of 4-byte words. 1 ...
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... R SDO SDI SCK SPI Memory R R Device S W HOLD Figure 12) ensures that a device is not selected if the M95256, M95256-W, M95256 SPI Memory SPI Memory R Device Device HOLD ...
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... M95256, M95256-W, M95256-R the transmission of an instruction), the clock line (C) must be connected to an external pull- down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled high): this ensures that S and C do not become high at the same time, and so, that the t 7 ...
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... Compliant with JEDEC Std J-STD-020C (for small body, Sn- assembly), the ST ECOPACK 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114 100 pF 1500 , R2 = 500 ). 26/43 M95256, M95256-W, M95256-R Table 6 may cause permanent damage to Parameter (2) Min ...
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... Supply voltage CC Ambient operating temperature (device grade Ambient operating temperature (device grade 3) 1. This product is under development. For more information, please contact your nearest ST sales office. Table 9. Operating conditions (M95256-R) Symbol V Supply voltage CC T Ambient operating temperature A 1. This product is under development. For more information, please contact your nearest ST sales office. ...
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... 5V open CC During t 2.5 V < 2.5 V < 2.5 V and and 2.5 V and and I CC M95256, M95256-W, M95256-R Min. Max Min. Max MHz ...
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... V Input low voltage IL V Input high voltage IH V Output low voltage OL V Output high voltage OH 1. Characterized value, not tested in production. Table 15. DC characteristics (M95256-R) Symbol Parameter I Input leakage current LI I Output leakage current LO I Supply current (Read) CC (2) I Supply current (Write) ...
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... Clock low setup time before HOLD not active Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output High-Z Write time M95256, M95256-W, M95256-R Table 10 and Table 7 Min. Max. D. ...
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... M95256, M95256-W, M95256-R Table 17. AC characteristics (M95256-W, device grade 6) Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ( CLL ( CLCH RC ( CHCL DVCH DSU t t CHDX ...
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... Clock low setup time before HOLD not active Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output High-Z Write time M95256, M95256-W, M95256-R and Table 8 Min. Max. Unit D.C. 5 MHz ...
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... M95256, M95256-W, M95256-R Table 19. AC characteristics (M95256-R) Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ( CLL ( CLCH RC ( CHCL DVCH DSU t t CHDX DH t HHCH ...
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... DC and AC parameters Figure 15. Serial input timing S tCHSL C tDVCH D Q Figure 16. Hold timing HOLD 34/43 tSLCH tCHDX MSB IN High Impedance tHLCH tCLHL tHLQZ M95256, M95256-W, M95256-R tSHSL tCHSH tSHCH tCHCL tCLCH LSB IN AI01447C tHHCH tCLHH tHHQV AI01448B ...
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... M95256, M95256-W, M95256-R Figure 17. Output timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D tCH tCLQV tQLQH tQHQL DC and AC parameters tCL tSHQZ LSB OUT AI01449e 35/43 ...
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... E 1 millimeters Typ Min Max 1.75 0.1 0.25 1.25 0.28 0.48 0.17 0.23 0.1 4.9 4 5.8 6.2 3.9 3 0.25 0.5 0° 8° 0.4 1.27 1.04 M95256, M95256-W, M95256 45˚ c 0.25 mm GAUGE PLANE SO-A (1) inches Typ Min 0.0039 0.0492 0.011 0.0067 0.1929 0.189 0.2362 0.2283 0.1535 0.1496 0.05 - 0.0098 0° 0.0157 0.0409 ® Max 0.0689 0.0098 0.0189 ...
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... M95256, M95256-W, M95256-R Figure 19. SO8 wide – 8 lead plastic small outline, 200 mils body width, package outline 1. Drawing is not to scale. Table 21. SO8 wide – 8 lead plastic small outline, 200 mils body width, package mechanical data Symbol Typ 0 ...
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... M95256, M95256-W, M95256 TSSOP8AM (1) inches Typ Min Max 0.0472 0.0020 0.0059 0.0394 0.0315 0.0413 0.0075 0.0118 0.0035 0.0079 0.0039 ...
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... M95256, M95256-W, M95256-R 11 Part numbering Table 23. Ordering information scheme Example: Device type M95 = SPI serial access EEPROM Device function 256 = 256 Kbit (32768 x 8) Operating voltage blank = V = 4 2 1 Package MN = SO8 (150 mils width SO8 (200 mils width) ...
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... Part numbering Table 24. Available M95256x products (package, voltage range, temperature grade) Package SO8N (MN) SO8W (MW) TSSOP (DW) 40/43 M95256 M95256-W (4 5 5.5 V) Range 3 Range 6, Range 3 - Range 6 - Range 6, Range 3 M95256, M95256-W, M95256-R M95256-R (1 5.5 V) Range 6 - Range 6 ...
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... M95256, M95256-W, M95256-R 12 Revision history Table 25. Document revision history Date Revision 17-Nov-1999 07-Feb-2000 22-Feb-2000 15-Mar-2000 29-Jan-2001 12-Jun-2001 08-Feb-2002 09-Aug-2002 24-Feb-2003 26-Jun-2003 2.10 21-Nov-2003 17-Mar-2004 21-Oct-2004 13-Apr-2006 New -V voltage range added (including the tables for DC characteristics, 2.1 AC characteristics, and ordering information). New -V voltage range extended to M95256 (including AC characteristics, 2 ...
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... Section 3.8: Supply voltage (VCC) Frequency corrected on page 8 V and V modified in Table 15: DC characteristics Process added to Table 23: Ordering information M95256, M95256-W, M95256-R Changes Section 3.8: Supply voltage (VCC) (WRSR), Section 5.5: Read from Section 5.6.1: ECC (error correction code) and ratings. and I , and V min modified in CC0 CC1 IH 3) ...
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... M95256, M95256-W, M95256-R Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...