M95256-CS3G/A STMICROELECTRONICS [STMicroelectronics], M95256-CS3G/A Datasheet
M95256-CS3G/A
Related parts for M95256-CS3G/A
M95256-CS3G/A Summary of contents
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... Enhanced ESD Protection ■ Packages ® – ECOPACK2 (RoHS compliant and Halogen-free) September 2010 M95256 M95256-W M95256-R 256 Kbit serial SPI bus EEPROM with high-speed clock Doc ID 12276 Rev 11 M95256-DR SO8 (MN) 150 mil width SO8 (MW) 200 mil width TSSOP8 (DW) ...
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... Write Disable (WRDI 5.3 Read Status Register (RDSR 5.3.1 5.3.2 5.3.3 5.3.4 5.4 Write Status Register (WRSR 5.5 Read from Memory Array (READ 5.6 Write to Memory Array (WRITE 2/48 M95256-DR, M95256, M95256-W, M95256 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Doc ID 12276 Rev 11 ...
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... M95256-DR, M95256, M95256-W, M95256-R 5.6.1 5.7 Read Identification Page (available only in M95256-DR devices 5.8 Write Identification Page (available only in M95256-DR devices 5.9 Read Lock Status (available only in M95256-DR devices 5.10 Lock ID (available only in M95256-DR devices Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters ...
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... Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 13. DC characteristics (M95256, device grade 3 Table 14. DC characteristics (M95256-W, device grade Table 15. DC characteristics (M95256-W, device grade Table 16. DC characteristics (M95256-R, M95256-DR, device grade Table 17. AC characteristics (M95256, device grade Table 18. AC characteristics, new M95256-W, device grade Table 19 ...
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... SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 39 Figure 24. SO8 wide – 8 lead plastic small outline, 200 mils body width, package outline . . . . . . . . . 40 Figure 25. TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 26. M95256-DR WLCSP, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Doc ID 12276 Rev 11 List of figures 5/48 ...
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... They are accessed by a high speed SPI- compatible bus. Their memory array is organized as 32768 × 8 bits. The M95256-DR also offers an additional page, named the Identification Page (64 bytes) which can be written and (later) permanently locked in Read-only mode. This Identification ...
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... M95256-DR, M95256, M95256-W, M95256-R Figure 3. WLCSP connections (top view, marking side, with balls on the underside) Table 1. Signal names Signal name HOLD HOLD Function Serial Clock Serial Data input Serial Data output Chip Select ...
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... Memory organization The memory is organized as shown in Figure 4. Block diagram HOLD W Control Logic Address Register and Counter 8/48 M95256-DR, M95256, M95256-W, M95256-R Figure 4. High Voltage Generator I/O Shift Register Data Register 1 Page X Decoder Doc ID 12276 Rev 11 Status Register Size of the Read only ...
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... M95256-DR, M95256, M95256-W, M95256-R 3 Signal description See Figure 1: Logic diagram connected to this device. 3.1 Serial Data output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). 3.2 Serial Data input (D) This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written ...
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... CC and Table 10). 3.8.2 Power-up conditions When the power supply is turned on, V time, the Chip Select (S) line is not allowed to float but should follow the V 10/48 M95256-DR, M95256, M95256-W, M95256-R supply voltage range must be applied (see CC(min) CC(max) 10). ...
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... M95256-DR, M95256, M95256-W, M95256-R therefore recommended to connect the S line to V Figure 17). In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge sensitive as well as level sensitive: after power-up, the device does not become selected until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select (S) must have been High, prior to going Low to start the first operation ...
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... Operating features Figure 5. Hold condition activation C HOLD 12/48 M95256-DR, M95256, M95256-W, M95256-R Hold Condition Doc ID 12276 Rev 11 Hold Condition AI02029D ...
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... M95256-DR, M95256, M95256-W, M95256-R 4.2 Status Register Figure 4 shows the position of the Status Register in the control logic of the device. The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. For a detailed description of the Status Register bits, see Section 5 ...
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... Read Lock Status Lock ID 1. Address bit A10 must be 0, all other address bits are Don't Care. 2. Address bit A10 must be 1, all other address bits are Don't Care. 14/48 M95256-DR, M95256, M95256-W, M95256-R Description Write Enable Write Disable Read Status Register ...
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... M95256-DR, M95256, M95256-W, M95256-R 5.1 Write Enable (WREN) The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in Figure and the bits of the instruction byte are shifted in, on Serial Data input (D). The device then enters a wait state ...
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... Status Register (SRWD, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. Table 5. Status Register format b7 SRWD Status Register Write Protect 16/48 M95256-DR, M95256, M95256-W, M95256-R Table 5) becomes protected against Write Doc ID 12276 Rev 11 Figure 8 ...
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... M95256-DR, M95256, M95256-W, M95256-R Figure 8. Read Status Register (RDSR) sequence High Impedance Instruction Status Register Out MSB Doc ID 12276 Rev 11 Instructions Status Register Out MSB ...
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... As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in 18/48 M95256-DR, M95256, M95256-W, M95256-R Figure 9. (as specified and is 0 when the Write cycle is completed. The WEL bit (Write Enable W is completed. W Table 2 ...
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... M95256-DR, M95256, M95256-W, M95256-R The protection features of the device are summarized in When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state possible to write to the Status Register (provided that the WEL bit has previously been set by a WREN instruction), regardless of the logic level applied on the Write Protect (W) input pin ...
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... Figure 10. Read from Memory Array (READ) sequence High Impedance Q 1. The most significant address bit (b15) is Don’t Care. 20/48 M95256-DR, M95256, M95256-W, M95256-R 10, to send this instruction to the device, Chip Select (S) is first driven ...
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... M95256-DR, M95256, M95256-W, M95256-R 5.6 Write to Memory Array (WRITE) As shown in Figure low. The bits of the instruction byte, address bytes, and at least one data byte are then shifted in, on Serial Data input (D). The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input data. The self-timed Write cycle, triggered by the rising ...
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... ECC bits), that is, the addressed byte is cycled together with the three other bytes making up the word therefore recommended to write data in words (4 bytes) in order to optimize the number of Write cycles. The M95256 and M95256-D devices are qualified at 1 million (1 000 000) Write cycles, using a cycling routine that writes to the device in multiples of 4-byte words. 22/48 ...
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... M95256-DR, M95256, M95256-W, M95256-R 5.7 Read Identification Page (available only in M95256-DR devices) The Identification Page (64 bytes additional page which can be written and (later) permanently locked in Read-only mode. Reading this page is achieved with the Read Identification Page instruction (see The Chip Select signal (S) is first driven low, the bits of the instruction byte and address bytes are then shifted in, on Serial Data input (D) ...
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... Instructions 5.8 Write Identification Page (available only in M95256-DR devices) The Identification Page (64 bytes additional page which can be written and (later) permanently locked in Read-only mode. Writing this page is achieved with the Write Identification Page instruction (see Chip Select signal (S) is first driven low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in on Serial Data input (D) ...
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... M95256-DR, M95256, M95256-W, M95256-R 5.9 Read Lock Status (available only in M95256-DR devices) The Read Lock Status instruction (see locked (or not) in read-only mode. The Read Lock Status sequence is defined with the Chip Select (S) first driven low. The bits of the instruction byte and address bytes are then shifted in on Serial Data input (D) ...
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... Chip Select (S) being driven high byte boundary (after the eighth bit, b0, of the last data byte that was latched in) ● if the Identification page is locked by the Lock Status bit Figure 16. Lock ID sequence 26/48 M95256-DR, M95256, M95256-W, M95256-R Doc ID 12276 Rev 11 ...
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... M95256-DR, M95256, M95256-W, M95256-R 6 Delivery state The device is delivered with the memory array set at all 1s (FFh). The Status Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized Connecting to the SPI bus These devices are fully compatible with the SPI protocol. ...
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... C remains at 1 for (CPOL=1, CPHA=1) Figure 18. SPI modes supported CPOL CPHA 28/48 M95256-DR, M95256, M95256-W, M95256-R requirement is met. The typical value 100 k. SHCH Figure MSB Doc ID 12276 Rev 11 18, is the clock polarity when the MSB AI01438B ...
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... M95256-DR, M95256, M95256-W, M95256-R 8 Maximum rating Stressing the device outside the ratings listed in the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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... Ambient operating temperature (device grade 3) A Table 9. Operating conditions (M95256-W) Symbol V Supply voltage CC Ambient operating temperature (device grade Ambient operating temperature (device grade 3) Table 10. Operating conditions (M95256-R and M95256-DR) Symbol V Supply voltage CC T Ambient operating temperature A Table 11. AC measurement conditions Symbol C Load capacitance ...
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... Figure 19. AC measurement I/O waveform Table 12. Capacitance Symbol C Output capacitance (Q) OUT Input capacitance ( Input capacitance (other pins) 1. Sampled only, not 100% tested. Table 13. DC characteristics (M95256, device grade 3) Symbol Parameter I Input leakage current LI I Output leakage current LO I Supply current CC Supply current ...
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... DC and AC parameters Table 14. DC characteristics (M95256-W, device grade 6) Symbol I Input leakage current LI I Output leakage current LO I Supply current (Read) CC (3) I Supply current (Write) CC0 Supply current I CC1 (Standby Power mode) V Input low voltage IL V Input high voltage IH V Output low voltage ...
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... OH 1. New product identified with process letter the application uses the M95256-R, M95256-DR device with 2.5 V < VCC < 5.5 V and -40 °C < TA < +85 °C, please refer to Table 14: DC characteristics (M95256-W, device grade for the new product identified with the process letter K (Preliminary data). ...
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... DC and AC parameters Table 17. AC characteristics (M95256, device grade 3) Test conditions specified in Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ( CLL ( CLCH RC ( CHCL DVCH DSU ...
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... M95256-DR, M95256, M95256-W, M95256-R Table 18. AC characteristics, new M95256-W, device grade 6 Test conditions - °C A Symbol Alt Clock frequency C SCK active setup time SLCH CSS1 not active setup time SHCH CSS2 deselect time SHSL ...
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... DC and AC parameters Table 19. AC characteristics (M95256-W, device grade 3) Test conditions specified in Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ( CLL ( CLCH RC ( CHCL DVCH DSU ...
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... New products are identified by process letter K. For these new products, the test flow guarantees the AC parameter values defined in this table (when V = 1.8 V) and the AC parameter values defined in CC 5.0 V). The M95256-DR is available as only "new product" type must never be less than the shortest possible clock period ...
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... D Q Figure 21. Hold timing HOLD Figure 22. Output timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D 38/48 M95256-DR, M95256, M95256-W, M95256-R tSLCH tCHDX MSB IN High Impedance tHLCH tCLHL tHLQZ tCH tCLQV Doc ID 12276 Rev 11 tSHSL tCHSH tSHCH tCHCL tCLCH LSB IN AI01447C tHHCH ...
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... M95256-DR, M95256, M95256-W, M95256-R 10 Package mechanical data In order to meet environmental requirements, ST offers the M95256 in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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... SO8 wide – 8 lead plastic small outline, 200 mils body width, package mechanical data Symbol Typ 0 Values in inches are converted from mm and rounded to 4 decimal digits. 40/48 M95256-DR, M95256, M95256-W, M95256 millimeters Min Max 2.5 0 0.25 1.51 2 0.35 0.51 0.1 ...
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... M95256-DR, M95256, M95256-W, M95256-R Figure 25. TSSOP8 – 8 lead thin shrink small outline, package outline Drawing is not to scale. Table 23. TSSOP8 – 8 lead thin shrink small outline, package mechanical data Symbol Values in inches are converted from mm and rounded to 4 decimal digits. ...
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... Package mechanical data Figure 26. M95256-DR WLCSP, 0.5 mm pitch, package outline Drawing is not to scale. Table 24. M95256-DR WLCSP, 0.5 mm pitch, package mechanical data Symbol A 0.60 A1 0.245 A2 0.355 B D 1.97 E 1.785 e 0.5 e1 0.866 e2 0.25 e3 0.433 F 0.552 G 0.392 ( Values in inches are converted from mm and rounded to 4 decimal digits. ...
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... M95256-DR, M95256, M95256-W, M95256-R 11 Part numbering Table 25. Ordering information scheme Example: Device type M95 = SPI serial access EEPROM Device function 256 = 256 Kbit 256-D = 256 Kbit plus Identification page Operating voltage blank = V = 4 2 1 Package MN = SO8 (150 mils width) ...
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... The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Table 26. Available M95256x products (package, voltage range, temperature grade) Package SO8N (MN) SO8W (MW) ...
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... New -V voltage range added (including the tables for DC characteristics, 2.1 AC characteristics, and ordering information). New -V voltage range extended to M95256 (including AC characteristics, 2.2 and ordering information). 2.3 tCLCH and tCHCL, for the M95xxx-V, changed from 1s to 100ns 2.4 -V voltage range changed to 2.7-3.6V Lead Soldering Temperature in the Absolute Maximum Ratings table amended 2 ...
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... W characteristics (M95256-DR, M95256-R device grade Blank option removed below Plating technology, process A modified and process V removed in Table 25: Ordering information Table 26: Available M95256x products (package, voltage range, temperature grade) added. SO8N and SO8W package specifications updated (see Package mechanical data). Package mechanical data: inches calculated from mm and rounded to 3 decimal digits ...
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... Table 20: AC characteristics (M95256-DR, M95256-R device grade 6) Updated Section 1: Description. Updated Section 5.7: Read Identification Page (available only in M95256- DR devices). 11 Updated Section 5.8: Write Identification Page (available only in M95256- DR devices). Updated Section 5.9: Read Lock Status (available only in M95256-DR devices). Doc ID 12276 Rev 11 Revision history Changes ) CC ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 48/48 M95256-DR, M95256, M95256-W, M95256-R Please Read Carefully: © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies www ...