AT26DF041-MU ATMEL [ATMEL Corporation], AT26DF041-MU Datasheet - Page 4

• Manufacturer Part Number: AT26DF041-MU
• Description: 4-MEGABIT 3.0-VOLT ONLY OR 2.7-VOLT ONLY SERIAL FIRMWARE DATAFLASH-R
• Manufacturer: ATMEL [ATMEL Corporation]

5. Device Operation
5.1
5.1.1
5.1.2
4
Read Commands
AT26DF041
Continuous Array Read
Status Register Read
The device operation is controlled by instructions from a host processor. The list of instructions
and their associated opcodes are contained in Tables 1 through 3. A valid instruction starts
with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or
main memory address location. While the CS pin is low, toggling the SCK pin controls the
loading of the opcode and the desired buffer or main memory address location through the SI
(serial input) pin. All instructions, addresses and data are transferred with the most significant
bit (MSB) first.
Main memory addressing is referenced using the terminology A23 - A0.
By specifying the appropriate opcode, data can be read from the main memory or from either
one of the two data buffers.
The Continuous Array Read command can be used to sequentially read a continuous stream
of data from the device by simply providing a clock signal once the initial starting address has
been specified. The device incorporates an internal address counter that automatically incre-
ments on every clock cycle.
Two opcodes, 0BH and 03H, can be used for the Continuous Array Read command. The use
of each opcode depends on the maximum SCK frequency that will be used to read data from
the device. The 0BH opcode can be used at any SCK frequency up to the maximum specified
by f
mum specified by f
To perform a Continuous Array Read, the CS pin must first be asserted and the appropriate
opcode must be clocked in. After the opcode has been clocked in, three address bytes (24 bits
representing A23 - A0) must be clocked in to specify the starting address location of the first
byte to read within the memory array. Since the upper address limit of the device is 07FFFFh,
the first five address bits (A23 - A19) will be ignored. If the 0BH opcode is used, one don't care
byte must also be clocked in after the three address bytes.
After the three address bytes (and the one don't care byte if using opcode 0BH) have been
clocked in, additional pulses on the SCK pin will result in serial data being output on the SO
(serial output) pin. The data is always output with the most-significant bit (MSB) of a byte first.
When the last bit of the memory array has been read, the device will continue reading back at
the beginning of the array (000000h). No delays will be incurred when wrapping around from
the end of the array to the beginning of the array.
Deasserting the CS pin (a low-to-high transition) will terminate the read operation and put the
SO pin into a high-impedance state. The Continuous Array Read command bypasses both
data buffers and leaves the contents of the buffers unchanged.
The status register can be used to determine the device’s Ready/Busy status or the device
density. To read the status register, an opcode of 05H must be loaded into the device. After
the last bit of the opcode is shifted in, the eight bits of the status register, starting with the MSB
(bit 7), will be shifted out on the SO pin during the next eight clock cycles. After bit 0 of the sta-
tus register has been shifted out, the sequence will repeat itself (as long as CS remains low
CAR1
. The 03H opcode can be used for lower frequency read operations up to the maxi-
CAR2
.
3495B–DFLSH–8/05