AT45DB011D-MU ATMEL [ATMEL Corporation], AT45DB011D-MU Datasheet - Page 7

• Manufacturer Part Number: AT45DB011D-MU
• Description: 1-megabit 2.7-volt DataFlash
• Manufacturer: ATMEL [ATMEL Corporation]

6.5
7. Program and Erase Commands
7.1
7.2
3639B–DFLASH–02/07
Buffer Read
Buffer Write
Buffer to Main Memory Page Program with Built-in Erase
reached, the device will continue reading back at the beginning of the same page. A low-to-high
transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The
maximum SCK frequency allowable for the Main Memory Page Read is defined by the f
specification. The Main Memory Page Read bypasses the data buffer and leaves the contents of
the buffer unchanged.
The SRAM data buffer can be accessed independently from the main memory array, and utiliz-
ing the Buffer Read Command allows data to be sequentially read directly from the buffer. Two
opcodes, D4H or D1H, can be used for the Buffer Read Command. The use of each opcode
depends on the maximum SCK frequency that will be used to read data from the buffer. The
D4H opcode can be used at any SCK frequency up to the maximum specified by f
opcode can be used for lower frequency read operations up to the maximum specified by f
To perform a buffer read from the DataFlash standard buffer (264 bytes), the opcode must be
clocked into the device followed by three address bytes comprised of 15 don’t care bits and
9 buffer address bits (BFA8 - BFA0). To perform a buffer read from the binary buffer (256 bytes),
the opcode must be clocked into the device followed by three address bytes comprised of
16 don’t care bits and 8 buffer address bits (BFA7 - BFA0). Following the address bytes, one
don’t care byte must be clocked in to initialize the read operation. The CS pin must remain low
during the loading of the opcode, the address bytes, the don’t care bytes, and the reading of
data. When the end of a buffer is reached, the device will continue reading back at the beginning
of the buffer. A low-to-high transition on the CS pin will terminate the read operation and tri-state
the output pin (SO).
Data can be clocked in from the input pin (SI) into the buffer. To load data into the DataFlash
standard buffer (264 bytes), a 1-byte opcode, 84H, must be clocked into the device followed by
three address bytes comprised of 15 don’t care bits and 9 buffer address bits (BFA8 - BFA0).
The 9 buffer address bits specify the first byte in the buffer to be written. To load data into the
binary buffers (256 bytes each), a 1-byte opcode, 84H, must be clocked into the device followed
by three address bytes comprised of 16 don’t care bits and 8 buffer address bits (BFA7 - BFA0).
The 8 buffer address bits specify the first byte in the buffer to be written. After the last address
byte has been clocked into the device, data can then be clocked in on subsequent clock cycles.
If the end of the data buffer is reached, the device will wrap around back to the beginning of the
buffer. Data will continue to be loaded into the buffer until a low-to-high transition is detected on
the CS pin.
Data written into the buffer can be programmed into the main memory. A 1-byte opcode, 83H,
must be clocked into the device. For the DataFlash standard page size (264 bytes), the opcode
must be followed by three address bytes consist of 5 don’t care bits, 9 page address bits
(PA8 - PA0) that specify the page in the main memory to be written and 9 don’t care bits. To per-
form a buffer to main memory page program with built-in erase for the binary page size (256
bytes), the opcode 83H must be clocked into the device followed by three address bytes consist-
ing of 7 don’t care bits, 9 page address bits (A16 - A8) that specify the page in the main memory
to be written and 8 don’t care bits. When a low-to-high transition occurs on the CS pin, the part
AT45DB011D [Preliminary]
CAR1
. The D1H
CAR2
SCK
.
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