AT45DB081D ATMEL [ATMEL Corporation], AT45DB081D Datasheet
AT45DB081D
Available stocks
Related parts for AT45DB081D
AT45DB081D Summary of contents
Page 1
... Green (Pb/Halide-free/RoHS Compliant) Packaging Options 1. Description The AT45DB081D is a 2.5V or 2.7V, serial-interface Flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage applications. The AT45DB081D supports RapidS serial interface for applications requiring very high speed operations. RapidS serial interface is SPI compatible for frequencies MHz ...
Page 2
... To allow for simple in-system reprogrammability, the AT45DB081D does not require high input voltages for programming. The device operates from a single power supply, 2.5V to 3.6V or 2.7V to 3.6V, for both the program and read operations. The AT45DB081D is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK) ...
Page 3
... Ground: The ground reference for the power supply. GND should be connected to the system GND ground. 3596E–DFLASH–02/07 pin is used to supply the source voltage to the device. CC voltages may produce spurious results and should not be attempted. CC AT45DB081D Asserted State Type Low Input – Input – ...
Page 4
... GND 4. Memory Array To provide optimal flexibility, the memory array of the AT45DB081D is divided into three levels of granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page by page basis. The erase operations can be performed at the chip, sector, block or page level ...
Page 5
... SCK pin will result in data being output on the SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care bytes, and the reading of data. When the end of a page in main memory is reached during a 3596E–DFLASH–02/07 AT45DB081D Table 15-1 on page 28 through Table 15-7 on ...
Page 6
... When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred AT45DB081D 6 specification. The Continuous Array Read bypasses both data buffers and leaves the specification ...
Page 7
... When the end of a buffer is reached, the device will continue reading back at the beginning of the buffer. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). 3596E–DFLASH–02/07 . The D1H and D3H opcode can be used for lower frequency CAR1 . CAR2 AT45DB081D 7 ...
Page 8
... It is necessary that the page in main memory that is being programmed has been previously erased using one of the erase commands (Page Erase or Block Erase). The programming of the page is internally self-timed and should take place in a maximum time of t status register will indicate that the part is busy. AT45DB081D 8 . During this time, EP ...
Page 9
... AT45DB081D PA3/ PA2/ PA1/ PA0/ A11 A10 • • • • • ...
Page 10
... The erase operation is internally self-timed and should take place in a time of t The Chip Erase command will not affect sectors that are protected or locked down; the contents of those sectors will remain unchanged. Only those sectors that are not protected or locked down will be erased. AT45DB081D 10 PA7/ PA6/ PA5/ ...
Page 11
... Status Register. 3596E–DFLASH–02/07 Chip Erase CS Opcode SI Byte 1 Each transition represents 8 bits Refer to errata regarding Chip Erase on AT45DB081D Byte 1 Byte 2 Byte 3 C7H 94H 80H Opcode Opcode Opcode Byte 2 ...
Page 12
... Disable Sector Protection commands. If the device is power cycled, then the software controlled protection will be disabled. Once the device is powered up, the Enable Sector Protection command should be reissued if sector pro- tection is desired and if the WP pin is not used. AT45DB081D 12 Byte 1 3DH Enable Sector Protection ...
Page 13
... When the WP pin is deasserted; however, the sector protection WPE 2 Disable Sector Command Protection Command – Issue Command Issue Command X Not Issued Yet or 2 Issue Command – Issue Command AT45DB081D , then the content of the Sector CC time) as long as the Enable Sec- WPD 3 Sector Protection Status X Disabled Disabled – Enabled X Enabled ...
Page 14
... Sector Protection Register.: Table 9-2. Sector Number Protected Unprotected Table 9-3. Sectors 0a, 0b Unprotected Protect Sector 0a Protect Sector 0b (Page 8-255) Protect Sectors 0a (Page 0-7), 0b (Page 8-255) Note: AT45DB081D 14 Sector Protection Register Sector 0 (0a, 0b) 0a (Page 0-7) Bit (1) 1. The default value for bytes 0 through 15 when shipped from Atmel x = don’ ...
Page 15
... Command Erase Sector Protection Register Figure 9-2. 3596E–DFLASH–02/07 Byte 1 3DH Erase Sector Protection Register CS Opcode Opcode SI Byte 1 Byte 2 Each transition represents 8 bits AT45DB081D PE Byte 2 Byte 3 Byte 4 2AH 7FH Opcode Opcode Byte 3 Byte 4 , during CFH 15 ...
Page 16
... Command Program Sector Protection Register Figure 9-3. Program Sector Protection Register CS Opcode SI Byte 1 Each transition represents 8 bits AT45DB081D 16 , during which time the Status Register will indicate that the device is busy Opcode Opcode Opcode Data Byte Byte 2 Byte 3 Byte 4 Section 9 ...
Page 17
... Instead, a combination of temporarily unprotecting individual sectors along with dis- abling sector protection completely will need to be implemented by the application to ensure that the limit of 10,000 cycles is not exceeded. 3596E–DFLASH–02/ Dummy Byte AT45DB081D Byte 1 Byte 2 Byte 3 32H xxH xxH Data Byte ...
Page 18
... Sector Lockdown Register to determine the status of the appropriate sector lockdown bits or bytes and reissue the Sector Lockdown com- mand if necessary. Command Sector Lockdown Figure 10-1. Sector Lockdown CS Opcode SI Byte 1 Each transition represents 8 bits AT45DB081D 18 Byte 1 3DH Opcode Opcode Opcode Address Byte 2 Byte 3 Byte 4 Bytes ...
Page 19
... Each transition represents 8 bits 3596E–DFLASH–02/07 Sector 0 (0a, 0b) (Page 0-7) Bit 7, 6 details the values read from the Sector Lockdown Register. Sector Lockdown Register xx = Dummy Byte Data Byte AT45DB081D 0 (0a, 0b) See Below 0a 0b (Page 8-255) Bit 5, 4 Bit ...
Page 20
... Therefore, the contents of the buffer 1 will be altered from its previous state when this command is issued. Figure 10-3. Program Security Register CS Opcode SI Byte 1 Each transition represents 8 bits AT45DB081D 20 Security Register • • • One-time User Programmable , during which time the Status Register will indicate that the device is busy. If the device P ...
Page 21
... SO pins. Deasserting the CS pin will terminate the Read Security Register operation and put the SO pin into a high-impedance state. Figure 10-4. Read Security Register CS SI Opcode SO Each transition represents 8 bits 3596E–DFLASH–02/ Data Byte n AT45DB081D Data Byte Data Byte ...
Page 22
... The operation is internally self-timed and should take place in a maximum time of t During this time, the status register will indicate that the part is busy. AT45DB081D 22 ), the status register can be read to determine whether the XFR ), the status register will indicate that the part is busy ...
Page 23
... The device density is indicated using bits and 2 of the status register. For the AT45DB081D, the four bits are 1001 The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of DataFlash devices ...
Page 24
... RDPD down, the device will return to the normal standby mode. Command Resume from Deep Power-down Figure 12-2. Resume from Deep Power-Down AT45DB081D 24 time. Once the device has entered the Deep Power-down mode, all instructions EDPD CS SI Each transition represents 8 bits time before the device can receive any commands ...
Page 25
... Extended Device Information String Length and any subsequent data is optional. 3596E–DFLASH–02/07 , during which time the Status Register will indicate that the device Opcode Opcode SI Byte 1 Byte 2 Each transition represents 8 bits AT45DB081D Byte 1 Byte 2 Byte 3 3DH 2AH 80H Opcode Opcode Byte 3 Byte 4 Byte 4 ...
Page 26
... Manufacturer ID codes that are two, three or even four bytes long with the first byte(s) in the sequence being 7FH. A system should detect code 7FH as a “Continuation Code” and continue to read Manufacturer ID bytes. The first non-7FH byte would signify the last byte of Manufacturer ID data. For Atmel (and some other manufacturers), the Manufacturer ID data is comprised of only one byte. AT45DB081D 26 Bit 3 ...
Page 27
... Group C can be executed. The Group B commands using buffer 1 should use Group C commands using buffer 2 and vice versa. Finally, during the internally self- timed portion of a Group D command, only the Status Register Read command should be executed. 3596E–DFLASH–02/07 AT45DB081D 27 ...
Page 28
... Buffer 1 to Main Memory Page Program without Built-in Erase Buffer 2 to Main Memory Page Program without Built-in Erase Page Erase Block Erase Sector Erase Chip Erase Main Memory Page Program Through Buffer 1 Main Memory Page Program Through Buffer 2 AT45DB081D 28 Read Commands Program and Erase Commands Opcode D2H E8H 03H ...
Page 29
... Note: 3596E–DFLASH–02/07 Protection and Security Commands Additional Commands (1) Legacy Commands 1. These legacy commands are not recommended for new designs. AT45DB081D Opcode 3DH + 2AH + 7FH + A9H 3DH + 2AH + 7FH + 9AH 3DH + 2AH + 7FH + CFH 3DH + 2AH + 7FH + FCH 32H 3DH + 2AH + 7FH + 30H ...
Page 30
... D7h E8h Notes Don’t Care AT45DB081D 30 Address Byte Address Byte ...
Page 31
... N/A N Don’t Care AT45DB081D Address Byte ...
Page 32
... The regulator needs to supply this peak current requirement. An under specified regulator can cause current starvation. Besides increasing system noise, current starvation during program- ming or erase can lead to improper operation and possible data corruption. AT45DB081D 32 . During power-up, the internal Power-on Reset circuitry keeps the device in ...
Page 33
... Notes during a buffer read maximum @ 20 MHz. CC1 2. All inputs are 5 volts tolerant. 3596E–DFLASH–02/07 *NOTICE: + 0.6V CC AT45DB081D (2.5V Version) Ind. -40°C to 85°C 2. the minimum specified datasheet value, the system should wait 10 ms before an opera- CC Condition CS, RESET all ...
Page 34
... Page Erase Time (256/264 bytes Block Erase Time (2,048/2,112 bytes Sector Erase Time (65,536/67,584 Chip Erase Time CE t RESET Pulse Width RST t RESET Recovery Time REC AT45DB081D 34 AT45DB081D (2.5V Version) AT45DB081D Min Typ Max Min 6.8 6.8 6.8 6.8 0.1 0.1 0.1 0 ...
Page 35
... MHz) of the RapidS serial case. 3596E–DFLASH–02/07 2.4V AC DRIVING 1.5V LEVELS 0.45V DEVICE UNDER TEST 30 pF period. These timing waveforms are valid over the full frequency range (max- WL AT45DB081D AC MEASUREMENT LEVEL page 36. Waveform 1 shows the SCK signal being ). Timing waveforms 1 and 2 conform ...
Page 36
... Waveform 2 – SPI Mode 3 Compatible (for Frequencies MHz) CS SCK HIGH 21.3 Waveform 3 – RapidS Mode SCK HIGH IMPEDANCE SO SI 21.4 Waveform 4 – RapidS Mode SCK HIGH AT45DB081D CSS VALID OUT VALID ...
Page 37
... Last bit of BYTE-MOSI is clocked into the slave. F. Slave clocks out first bit of BYTE-SO. G. Master clocks in first bit of BYTE-SO. H. Slave clocks out second bit of BYTE-SO. I. Master clocks in last bit of BYTE-SO. 3596E–DFLASH–02/ LSB BYTE-MOSI F AT45DB081D MSB BYTE- LSB 37 ...
Page 38
... Register Read, Manufacturer and Device ID Read) SI (INPUT) MSB 21.8 Command Sequence for Read/Write Operations for Page Size 264 Bytes (Except Status Register Read, Manufacturer and Device ID Read) SI (INPUT) MSB AT45DB081D 38 CMD 8 bits 8 bits Don’t Care ...
Page 39
... BINARY PAGE SIZE 16 DON'T CARE + BFA7-BFA0 X BFA7-0 X···X, BFA8 Starts self-timed erase/program operation BINARY PAGE SIZE A19- DON'T CARE BITS CMD PA10-7 AT45DB081D BUFFER 2 TO MAIN MEMORY PAGE PROGRAM BUFFER 2 (256/264 BYTES) BUFFER 2 WRITE Completes writing into selected buffer n n+1 ...
Page 40
... BUFFER 1 23.1 Main Memory Page Read CS SI (INPUT) CMD SO (OUTPUT) 23.2 Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer (INPUT) SO (OUTPUT) AT45DB081D 40 FLASH MEMORY ARRAY MAIN MEMORY READ PAGE READ I/O INTERFACE SO ADDRESS FOR BINARY PAGE SIZE A15-A8 A19-A16 A7-A0 ...
Page 41
... A X MSB MSB ADDRESS BITS A19 - MSB MSB AT45DB081D 1 Dummy Byte BFA7 DATA BYTE MSB BIT 2047/2111 OF PAGE n ...
Page 42
... MSB HIGH-IMPEDANCE SO 24.5 Buffer Read (Opcode D4H or D6H SCK OPCODE MSB HIGH-IMPEDANCE SO AT45DB081D OPCODE ADDRESS BITS A19- MSB ...
Page 43
... MSB OPCODE DON'T CARE MSB AT45DB081D DATA BYTE MSB MSB ...
Page 44
... CS 0 SCK MSB HIGH-IMPEDANCE SO 24.10 Status Register Read (Opcode D7H SCK SI 1 MSB HIGH-IMPEDANCE SO 24.11 Manufacturer and Device Read (Opcode 9FH) CS SCK SI HIGH-IMPEDANCE SO Note: Each transition AT45DB081D OPCODE DON'T CARE ...
Page 45
... The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. 3596E–DFLASH–02/07 START provide address (82H, 85H) END AT45DB081D and data BUFFER WRITE (84H, 87H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H, 86H) ...
Page 46
... Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to wait until 10,000 cumulative page erase and program operations have accumulated before rewriting all pages of the sector. See application note AN-4 (“Using Atmel’s Serial DataFlash”) for more details. AT45DB081D 46 START ...
Page 47
... Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8M1-A 8-lead Very Thin Micro Lead-frame Package (MLF) 3596E–DFLASH–02/07 Ordering Code AT45DB081D-SSU AT45DB081D-SU AT45DB081D-MU AT45DB081D-SSU-2.5 AT45DB081D-SU-2.5 AT45DB081D-MU-2.5 Package Type AT45DB081D Package Operation Range 8S1 8S2 8M1-A Industrial (-40°C to 85°C) ...
Page 48
... JEDEC SOIC TOP VIEW e e SIDE VIEW Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R AT45DB081D ...
Page 49
... TOP VIEW TOP VIEW SIDE VIEW SIDE VIEW TITLE 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) AT45DB081D θ θ END VIEW END VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A 1 ...
Page 50
... MLF BOTTOM VIEW 2325 Orchard Parkway San Jose, CA 95131 R AT45DB081D Pin 1 ID TOP VIEW A2 A 0.45 D2 Pin #1 Notch (0. TITLE 8M1-A, 8-pad 1.00 mm Body, Very Thin Dual Flat Package No Lead (MLF) SIDE VIEW A3 A1 0.08 C COMMON DIMENSIONS ...
Page 51
... Corrected PA3 in opcode 50h for addressing sequence with standard page size. Corrected Chip Erase opcode from 7CH to C7H. Clarified the commands B and C usage for operation mode. Removed Preliminary. Added errata regarding Chip Erase. Changed various timing parameters under Removed RDY/BUSY pin references. AT45DB081D Table 18-4. 51 ...
Page 52
... Use Block Erase (opcode 50H alternative. The Block Erase function is not affected by the Chip Erase issue. 29.1.3 Resolution The Chip Erase feature may be fixed with a new revision of the device. Please contact Atmel for the estimated availability of devices with the fix. AT45DB081D 52 3596E–DFLASH–02/07 ...
Page 53
... Atmel Corporation. All rights reserved. Atmel registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 ...