NCP1587 ONSEMI [ON Semiconductor], NCP1587 Datasheet - Page 10

• Manufacturer Part Number: NCP1587
• Description: Low Voltage Synchronous Buck Controller
• Manufacturer: ONSEMI [ON Semiconductor]

The upper (switching) MOSFET gate driver losses are:
Where:
The lower (synchronous) MOSFET gate driver losses are:
Where:
calculated as:
Where:
IC package.
specifications section of this data sheet and a calculation can
be made to determine the IC junction temperature. However,
it should be noted that the physical layout of the board, the
proximity of other heat sources such as MOSFETs and
inductors, and the amount of metal connected to the IC,
impact the temperature of the device. Use these calculations
as a guide, but measurements should be taken in the actual
application.
Layout Considerations
very important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. These interconnecting impedances should be
minimized by using wide, short printed circuit traces. The
critical components should be located as close together as
possible using ground plane construction or single point
grounding. The figure below shows the critical power
components of the converter. To minimize the voltage
overshoot the interconnecting wires indicated by heavy lines
should be part of ground or power plane in a printed circuit
board. The components shown in the figure below should be
located as close together as possible. Please note that the
capacitors C
capacitors. It is desirable to locate the NCP1587 within 1
inch of the MOSFETs, Q1 and Q2. The circuit traces for the
MOSFETs’ gate and source connections from the NCP1587
must be sized to handle up to 2 A peak current.
P
I
V
P
P
Q
f
V
Q
The junction temperature of the control IC can then be
T
T
θ
The package thermal resistance can be obtained from the
As in any high frequency switching converter, layout is
CC
SW
JA
IC
TG
BG
A
J
CC
TG
BST
BG
= the junction temperature of the IC,
= the ambient temperature,
= control IC power dissipation,
= IC measured supply current,
= the junction−to−ambient thermal resistance of the
= the switching frequency,
= top gate driver losses,
= bottom gate driver losses.
= IC supply voltage,
= total upper MOSFET gate charge at VBST,
= total lower MOSFET gate charge at V
= the BST pin voltage.
IN
and C
P
P
TG
BG
T
J
+ Q
OUT
+ Q
+ T
TG
each represent numerous physical
BG
A
) P
f
f
SW
IC
SW
q
V
JA
V
BST
CC
CC
.
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10
DESIGN EXAMPLE I: Type II Compensation
(Electrolytic Cap. with large ESR)
Choose the loop gain crossover frequency;
The corner frequency of the output filter is calculated below;
Check that the ESR zero frequency is not too high;
is necessary.
Choose C
gain magnitude, zero position and the soft start. By adjusting
the value of this compensation capacitor, the crossover
frequency and the soft start time can be adjusted.
Zero of the compensation network is calculated as follows;
Pole of the compensation network is calculated as follows;
C
C
Switching Frequency
Output Capacitance
Output Capacitance
Output Inductance
Input Voltage
Output Voltage
If ESR zero is larger than F
The compensation capacitor (C
The recommended compensation values are; R
= 100 nF, C
Figure 12. Components to be Considered for
F
LC
F
F
ESR
ESR
C
R
+
for the crossover frequency and the soft start
C
C
F
2
+
+
+
+
p
p
P
+
2
2
+ F
+
F
2
2
= 1000 pF
Layout Specifications
p
co
F
2
2
Z
+ 1
sw
p
p
+ F
p
p
C
5
+ 275 KHz
p
p
1 mH
C
1
R
45 mW
LC
F
2.65 kHz
1
1
+ 100 nF
ESR
2
z
1
F
F
275 kHz
+ 2.65 KHz
sw
p
co
1
1
C
1
/10, Type III compensation
3600 mF
+ 55 KHz
C
(1800 mF
R
C
C
C
O
) is related to the loop
F
R
C
L
V
V
SW
out
out
t
ESR
out
in
100 nF
600.6
= 12 V
F
+ 2.65 KHz
= 1 mH
= 1.6 V
10
= 2×1800 mF
= 275 KHz
co
= 45 mW/Each
2)
+ 600.6 W
+ 963.6 pF
+ 2 KHz
C
= 604,