LT3071EUFD LINER [Linear Technology], LT3071EUFD Datasheet - Page 20

• Manufacturer Part Number: LT3071EUFD
• Description: 5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator with Analog Margining
• Manufacturer: LINER [Linear Technology]

LT3071
ApplicAtions inFormAtion
the farther the wires are placed apart from each other, the
more inductance will be reduced, up to a 50% reduction
when placed a few inches apart. Splitting the wires basi-
cally connects two equal inductors in parallel. However,
when placed in close proximity from each other, mutual
inductance is added to the overall self inductance of the
wires. The most effective way to reduce overall inductance
is to place the forward and return-current conductors (the
wire for the input and the wire for the return ground) in
very close proximity. Two 18-AWG wires separated by
0.05 inch reduce the overall self inductance to about one-
fourth of a single isolated wire. If the LT3071 is powered
by a battery mounted in close proximity with ground and
power planes on the same circuit board, a 47µF input
capacitor is sufficient for stability. However, if the LT3071
is powered by a distant supply, use a low ESR, large value
input capacitor on the order of 330µF . As power supply
output impedance varies, the minimum input capacitance
needed for application stability also varies.
Bias Pin Capacitance Requirements
The BIAS pin supplies current to most of the internal
control circuitry and the output stage driving the pass
transistor. The LT3071 requires a minimum 2.2µF by-
pass capacitor for stability and proper operation. To
ensure proper operation, the BIAS voltage must sat-
isfy the following conditions: 2.2V ≤ V
V
minimum BIAS voltage is limited to 2.2V.
Load Regulation
The LT3071 provides a Kelvin sense pin for V
the application to correct for parasitic package and PCB
I-R drops. However, LTC recommends that the SENSE pin
terminate in close proximity to the LT3071’s OUT pins.
This minimizes parasitic inductance and optimizes regula-
tion. The LT3071 handles moderate levels of output line
impedance, but excessive impedance between V
C
and adversely affects stability.
0
BIAS
OUT
causes excessive phase shift in the feedback loop
≥ (1.25 • V
OUT
+ 1V). For V
OUT
BIAS
≤ 0.95V, the
OUT
≤ 3.6V and
, allowing
OUT
and
Figure 1 in the Pin Functions section illustrates the Kelvin-
Sense connection method that eliminates voltage drops
due to PCB trace resistance. However, note that the voltage
drop across the external PCB traces adds to the dropout
voltage of the regulator. The SENSE pin input bias current
depends on the selected output voltage. SENSE pin input
current varies from 50µA typically at V
typically at V
Short-Circuit and Overload Recovery
Like many IC power regulators, the LT3071 has safe op-
erating area (SOA) protection. The safe area protection
decreases current limit as input-to-output voltage increases
and keeps the power transistor inside a safe operating
region for all values of input-to-output voltage up to the
absolute maximum voltage rating. V
the UVLO threshold for any function. The LT3071 has a
precision current limit specified at ±20% that is active if
V
Under conditions of maximum I
V
3W. If ambient temperature is high enough, die junction
temperature will exceed the 125°C maximum operating
temperature. If this occurs, the LT3071 relies on two
additional thermal safety features. At about 145°C, the
PWRGD output pulls low providing an early warning of an
impending thermal shutdown condition. At 165°C typically,
the LT3071’s thermal shutdown engages and the output is
shut down until the IC temperature falls below the thermal
hysteresis limit. The SOA protection decreases current limit
as the IN-to-OUT voltage increases and keeps the power
dissipation at safe levels for all values of input-to-output
voltage. The LT3071 provides some output current at all
values of input-to-output voltage up to the absolute maxi-
mum voltage rating. See the Current Limit vs V
the Typical Performance Characteristics.
During start-up, after the BIAS voltage has cleared its UVLO
threshold and V
at the rate of current limit charging C
BIAS
IN
-V
is above UVLO.
OUT
the device’s power dissipation peaks at about
OUT
IN
= 1.8V.
is increasing, output voltage increases
LOAD
BIAS
OUT
OUT
and maximum
= 0.8V to 300µA
must be above
.
IN
curve in
3071f