HIP6004ACB INTERSIL [Intersil Corporation], HIP6004ACB Datasheet - Page 9

• Manufacturer Part Number: HIP6004ACB
• Description: Buck and Synchronous-Rectifier (PWM) Controller and Output Voltage Monitor
• Manufacturer: INTERSIL [Intersil Corporation]

F
Loop Gain is constructed on the log-log graph of Figure 8
by adding the Modulator Gain (in dB) to the Compensation
Gain (in dB). This is equivalent to multiplying the modulator
transfer function to the compensation transfer function and
plotting the gain.
The compensation gain uses external impedance networks
Z
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and voltage rating
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements. For example, Intel
recommends that the high frequency decoupling for the
Pentium Pro be composed of at least forty (40) 1 F ceramic
capacitors in the 1206 surface-mount package.
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
P2
FB
100
-20
-40
-60
80
60
40
20
with the capabilities of the error amplifier. The Closed
and Z
0
10
(R
20LOG
IN
2
MODULATOR
/R
to provide a stable, high bandwidth (BW) overall
1
GAIN
)
100
1K
F
Z1
F
FREQUENCY (Hz)
LC
F
Z2
2-70
10K
F
F
P1
ESR
(V
100K
IN
20LOG
F
/ V
P2
OSC
OPEN LOOP
ERROR AMP GAIN
1M
)
COMPENSATION
CLOSED LOOP
10M
GAIN
GAIN
HIP6004A
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient.
An aluminum electrolytic capacitor’s ESR value is related to
the case size with lower ESR available in larger case sizes.
However, the equivalent series inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient
loading. Unfortunately, ESL is not a specified parameter.
Work with your capacitor supplier and measure the
capacitor’s impedance with frequency to select a suitable
component. In most cases, multiple electrolytic capacitors of
small case size perform better than a single large case
capacitor.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
HIP6004A will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
where: I
response time to the application of load, and t
response time to the removal of load. With a +5V input
source, the worst case response time can be either at the
application or removal of load and dependent upon the
DACOUT setting. Be sure to check both of these equations
at the minimum and maximum output levels for the worst
t
RISE
I =
=
V
IN
TRAN
Fs x L
- V
V
L x I
IN
OUT
- V
is the transient load current step, t
TRAN
OUT
V
V
OUT
IN
t
FALL
V
OUT
=
L x I
=
V
OUT
I x ESR
TRAN
FALL
RISE
is the
is the