FDMF6821A FAIRCHILD [Fairchild Semiconductor], FDMF6821A Datasheet
FDMF6821A
Related parts for FDMF6821A
FDMF6821A Summary of contents
Page 1
... A thermal warning function warns of a potential over-temperature situation. The FDMF6821A also incorporates a Skip Mode (SMOD#) for improved light-load efficiency. The FDMF6821A also provides a 3-state 3.3 V PWM input for compatibility with a wide range of PWM controllers. Applications High-Performance Gaming Motherboards ...
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... UVLO DISB# 10µA V CIN R UP_PWM Input PWM 3- State Logic R DN_PWM THWN# Temp. Sense CGND © 2012 Fairchild Semiconductor Corporation FDMF6821A • Rev. 1.0.0 VDRV VCIN VIN R BOOT DISB# BOOT PWM FDMF6821A PHASE SMOD# VSWH THWN# PGND CGND Figure 1. Typical Application Circuit VDRV ...
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... LOW). This pin has a 10 µA internal pull-down current source. Do not add a noise filter capacitor. 40 PWM PWM signal input. This pin accepts a three-state 3.3 V PWM signal from the controller. © 2012 Fairchild Semiconductor Corporation FDMF6821A • Rev. 1.0.0 Figure 4. Top View Description 3 www.fairchildsemi.com ...
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... MOSFET switching transients. For reliable DrMOS operation, VSWH-to-GND and BOOT-to-GND must remain at or below the Absolute Maximum Ratings shown in the table above. Refer to the “Application Information” and “PCB Layout Guidelines” sections of this datasheet for additional information. © 2012 Fairchild Semiconductor Corporation FDMF6821A • Rev. 1.0.0 Parameter Referenced to CGND Referenced to CGND ...
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... High-Level Input Voltage IH_SMOD V Low-Level Input Voltage IL_SMOD I Pull-Up Current PLU t Propagation Delay PD_SLGLL t Propagation Delay PD_SHGLH © 2012 Fairchild Semiconductor Corporation FDMF6821A • Rev. 1.0 and +25°C unless otherwise noted. CIN DRV A J Condition PWM=LOW or HIGH or Float Q ...
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... PWM-HIGH Propagation t PD_PHGLL Delay Exiting 3-State Propagation t PD_TSGLH Delay Boot Diode V Forward-Voltage Drop F V Breakdown Voltage R © 2012 Fairchild Semiconductor Corporation FDMF6821A • Rev. 1.0 and +25°C unless otherwise noted. CIN DRV A J Condition PLD = +25°C) OUT ...
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... V IH_PWM PWM VSWH VSWH t PD PHGLL t D_DEADON © 2012 Fairchild Semiconductor Corporation FDMF6821A • Rev. 1.0.0 90% 1.0V 10% t PD_PLGHL Figure 5. PWM Timing Diagram 7 V IL_PWM 10% 90% 2.2V t D_DEADOFF www.fairchildsemi.com ...
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... Figure 8. Power Loss vs. Switching Frequency 1. 12V 1V 300kHz OUT SW 1.10 1.05 1.00 0.95 0.90 4.0 4.5 Driver Supply Voltage, V Figure 10. Power Loss vs. Driver Supply Voltage © 2012 Fairchild Semiconductor Corporation FDMF6821A • Rev. 1.0 =250 nH, T CIN DRV OUT 1000kHz ...
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... Driver Supply Voltage, V Figure 14. Driver Supply Current vs. Driver Supply Voltage 3.2 3.1 3.0 2.9 2.8 2.7 2.6 - Driver IC Junction Temperature, T Figure 16. UVLO Threshold vs. Temperature © 2012 Fairchild Semiconductor Corporation FDMF6821A • Rev. 1.0 =250 nH, T CIN DRV OUT 70 = 300kHz 1V 30A SW OUT OUT ...
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... Driver IC Junction Temperature, T Figure 20. SMOD# Threshold vs. Temperature 2 25°C A 2.0 1.8 1.6 1.4 1.2 4.50 4.75 5.00 Driver IC Supply Voltage, V Figure 22. DISB# Threshold vs. Driver Supply Voltage © 2012 Fairchild Semiconductor Corporation FDMF6821A • Rev. 1.0 =25°C, and natural convection cooling, unless otherwise specified. A 2.2 2.0 V IH_PWM 1.8 V TRI_HI V HIZ_PWM 1.6 V TRI_LO 1.4 V IL_PWM 1.2 ...
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... CIN 11.5 11.0 10.5 10.0 9.5 9.0 - Driver IC Junction Temperature, T Figure 24. DISB# Pull-Down Current vs. Temperature © 2012 Fairchild Semiconductor Corporation FDMF6821A • Rev. 1.0 =25°C, and natural convection cooling, unless otherwise specified. A 500 450 400 350 300 250 200 150 100 55 100 125 150 ...
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... PWM input goes from three-state to LOW, the low-side MOSFET is turned on. If the PWM input goes from Driver State three-state to HIGH, the high-side MOSFET is turned on. This is illustrated in Figure 27. The FDMF6821A design allows for short propagation delays when exiting the three-state window (see Electrical Characteristics). Low-Side Driver ...
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... PD_SHGLH GS IH_SMOD © 2012 Fairchild Semiconductor Corporation FDMF6821A • Rev. 1.0.0 HIGH, Q2 begins to turn off after a propagation delay (t PD_PHGLL Q1 begins to turn on after adaptive delay t To preclude overlap during the HIGH-to-LOW transition (Q1 off to Q2 on), the adaptive circuitry monitors the voltage at the GH-to-PHASE pin pair ...
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... D_DEADOFF D_DEADON © 2012 Fairchild Semiconductor Corporation FDMF6821A • Rev. 1.0.0 When the SMOD# pin is pulled HIGH, the synchronous buck converter works in Synchronous Mode. This mode allows for gating on the Low Side MOSFET. When the SMOD# pin is pulled LOW, the low-side MOSFET is gated off ...
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... ON Open - Drain Output © 2012 Fairchild Semiconductor Corporation FDMF6821A • Rev. 1.0.0 VCIN Filter The VDRV pin provides power to the gate drive of the high-side and low-side power MOSFET. In most cases, it can be connected directly to VCIN, the pin that provides power to the logic section of the driver. For additional noise immunity filter can be inserted between the VDRV and VCIN pins ...
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... MOSFET, balance using the largest area possible to improve DrMOS cooling while maintaining acceptable noise emission output inductor should be located close to the FDMF6821A to minimize the power loss due to the V copper trace. Care should also be taken so the SWH inductor dissipation does not heat the DrMOS. ® ...
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... Fairchild Semiconductor Corporation FDMF6821A • Rev. 1.0.0 Figure 31. PCB Layout Example (Top View) Figure 32. PCB Layout Example (Bottom View) 17 www.fairchildsemi.com ...
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... Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2012 Fairchild Semiconductor Corporation FDMF6821A • Rev. 1.0.0 B PIN#1 INDICATOR 6.00 ...
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... Fairchild Semiconductor Corporation FDMF6821A • Rev. 1.0.0 19 www.fairchildsemi.com ...