LM99CIMMX NSC [National Semiconductor], LM99CIMMX Datasheet - Page 12

• Manufacturer Part Number: LM99CIMMX
• Manufacturer: NSC [National Semiconductor]

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1.0 Functional Description
1.9.1 SMBus Timing Diagrams
LM99 Timing Diagram
1.10 SERIAL INTERFACE RESET
In the event that the SMBus Master is RESET while the
LM99 is transmitting on the SMBData line, the LM99 must be
returned to a known state in the communication protocol.
This may be done in one of two ways:
1. When SMBData is LOW, the LM99 SMBus state ma-
chine resets to the SMBus idle state if either SMBData
or SMBCLK are held low for more than 35 ms (t
EOUT
). Note that according to SMBus specification 2.0 all
(c) Serial Bus Read from a Register with the Internal Command Register preset to desired value.
(a) Serial Bus Write to the internal Command Register followed by a the Data Byte
(b) Serial Bus Write to the Internal Command Register
FIGURE 7. SMBus Timing Diagrams
(Continued)
TIM -
12
2. When SMBData is HIGH, have the master initiate an
devices are to timeout when either the SMBCLK or
SMBData lines are held low for 25-35 ms. Therefore, to
insure a timeout of all devices on the bus the SMBCLK
or SMBData lines must be held low for at least 35 ms.
SMBus start. The LM99 will respond properly to an
SMBus start condition at any point during the communi-
cation. After the start the LM99 will expect an SMBus
Address address byte.
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