LM80CIMT-5 NSC [National Semiconductor], LM80CIMT-5 Datasheet - Page 23

• Manufacturer Part Number: LM80CIMT-5
• Description: Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor
• Manufacturer: NSC [National Semiconductor]

Bit
0
1
2
3
4
5
6
7
Functional Description
12.3 Configuration Register — Address 00h
Power on default
Start
INT Enable
INT polarity
select
INT_Clear
RESET
Chassis Clear
GPO
INITIALIZATION
Name
<
7:0
>
= 00001000 binary
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/
Write
(Continued)
A one enables startup of monitoring operations, a zero puts the part in standby mode.
Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this
location after an interrupt has occurred unlike “INT_Clear” bit.At start up, limit checking
functions and scanning begin. Note, all limits should be set in the Value RAM before
setting this bit HIGH.
A one enables the INT Interrupt output.
A one selects an active high open source output while a zero selects an active low
open drain output.
A one disables the INT and RST_OUT/OS outputs without affecting the contents of
Interrupt Status Registers. The device will stop monitoring. It will resume upon clearing
of this bit.
A one outputs at least a 10 ms active low reset signal at RESET, if
<
has gone inactive.
A one clears the CI (Chassis Intrusion) pin. This bit clears itself after the CI pins
cleared.
A one in this bit drives a one on GPO (General Purpose Output) pin.
A one restores power on default value to the Configuration Register, Interrupt Status
Registers, Interrupt Mask Registers, Fan Divisor/RST_OUT/OSRegister, and the OS
Configuration/Temperature Resolution Register. This bit clears itself since the power
on default is zero.
6
>
= 0 in the Fan Divisor/RST_OUT/OS Register. This bit is cleared once the pulse
23
Description
<
7
>
= 1 and
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